Lab Final Project: Digital Receiver Design

By Bryan Callaway- Email: callab2@unlv.nevada.edu

Last edited: 11/17/2020

Task:

Design, layout, and simulate a digital receiver circuit that accepts a 

high-speed digital input signal D and Di (a differential pair connected to your circuit from, for example, a twisted pair of wires such as in an 

Ethernet cable). D and Di are complements so, for example, if D is 5V then Di is 0V and output = 1. Another example, when D is 1V and Di is 2V

then output = 0. At high-speeds and long distances the voltages received aren't full digital logic levels (i.e., 5V and 0V), hence the need to design, 

and use, a high-speed digital recevier circuit. Ideally, when D > Di the receiver outputs a 1. When D < Di the receiver outputs a 0. Base your 

design on the topology seen in Fig. 18.23. Try to design for high-speed and low-power. Characterize your design (in sims) and the trade-offs. 

For example, show that you get higher-speed if you use more energy (burn more power). See if you can get, in this 500 nm process, 250 Mbits/s

(a bit width of 4 ns) with an input voltage difference of, for example, 250 mV (with D and Di swinging back and forth between 2.75V and 3V, 

for one of many examples, your circuit outputs the correspondingly correct values). Note that while Fig. 18.23 shows one inverter on the output 

you may find, for example, that two inverters work better (at the cost of power). Use a table to summarize your design's performance.

Design:
For my digital receiver, I utilized the topology seen in Figure 18.23 of the fourth edition of Dr. Baker's CMOS: Circuit Design, Layout, and Simulations. This topology combines the n-flavor input buffer (Fig. 18.17) and p-flavor input buffer (Fig. 18.21) topologies in parallel in order to create a buffer that is strong and can work with many different operating voltages. I chose to utilize an additional 12/6 inverter in order to better square the signal at the output. All PMOS transistors are 12u/600n and all NMOS transistors are 6u/600n- except for two transistors... we'll come back to those!

Schematic:

Symbol:

Simulation Circuit:

When I simulated this circuit, I utilized two pulse sources which swung back and forth between two values. For some simulations I utilized a delay in one of my pulse sources, for other simulations I just had the second source have the opposite V1 and V2 of the first source.

Simulations:

I started by simulating the circuit for various choices of VDD. First I verified operation for VDD = 5V:

Next I verified operation for 4V:


Then 3V:

Then 2V:


It is clear to see that the receiver operates properly for a VDD of 4-5V.

Next, I simulated the circuit to see how it behaved for various choices of Vinp and Vinm.

2.5V to 3V:


2.75V to 3V:


2.9V to 3V:


2.95V to 3V:


2.97V to 3V:


2.99V to 3V:


It is clear that as the difference between the voltages our inputs are swinging between get smaller, the receiver does not work as well. It is also clear that for my design the minimum voltage difference that we can have and still achieve reasonable performance is around 50 mV.

The next simulation involved seeing how the circuit behaved for different input bit widths:

I started by verifying performance for a bit-width of 4ns:


Then 3ns:


2ns:


1ns:


5ns:



My design functions properly for the required bit width.

After this, I simulated the performance of my device for various operating temperatures:



It is clear to see that as temperature increases, our output becomes more curved and less squared.

Last but not least, I simulated my design for power usage:

PAVG = VDD*IAVG = Ctot*(VDD)^2*fclk. Thus, for inputs with smaller bit widths we should burn more power. A simpler way of saying this is that as the speed of the circuit increases, the power consumption should increase. Let's verify this!

Average Power for inputs with 4ns bit width (period 10ns -> f = 100 MHz):


In 40ns the device has an average power of 9mW for an input frequency of 100 MHz

Average power for inputs with 3ns bit width (Period 8ns -> f = 125 MHz):


In 40ns the device the device has an average power of roughly 9.2 mW for an input frequency of 125MHz


Remember those transistors I mentioned earlier? They're the transistors which have their gates tied up to other transistors for self-biasing purposes. By increasing their length, we can obtain better average power consumption for our circuit. This comes at the cost of decreasing the speed of the circuit:

(The length of the PMOS and NMOS discussed above have been changed to 6u. Now let's graph the power and calculate the average power!)


The spikes increased in our graph! This is because the circuit is charging faster. Let's see how our average power was inpacted!

In 40ns the device has an average power of 4.2mW for an input frequency of 125 MHz

We can see how increasing the L of these transistors impacts design performance by comparing the output of the receiver for our initial transistor values (600n) and the new values (6u):

2.97V to 3V for Long L Transistors:



2.97V to 3V for transistors with L=600n:


We can see that the second circuit is much faster!

Extracted:


LVS/DRC: