Lab 7: Using Buses and Arrays in the Design of Word Inverters, MUXes, and High-Speed Adders

By Bryan Callaway- Email: callab2@unlv.nevada.edu

Last edited: 10/31/2020

Lab description: In this lab, we utilized buses in the design of word inverters, MUXes, and High-Speed Adders. 

Prelab:
In the prelab, we designed a 31 stage ring oscillator. We started by creating a schematic:

Next, we created a symbol:

Then we created a layout for our design:


DRC/LVS:


Finally, we simulated our design:



Lab:
For the first experiment, I designed a 4-bit word inverter. I started this design by creating a schematic:

Next, I created a symbol:

Then I simulated my design:



The next experiment involved designing 8-bit input/output arrays for various gates. First, I actually made the gates which weren't created in the previous lab. This is where the versatility of the NAND gate was demonstrated. We know by De Morgan's Theorem that !(A&B) = !A|!B. Logically, a NAND gate takes the form !(A&B), thus, we can make any gate that we want with just NAND gates and inverters (we can even make an inverter from a NAND gate, all we have to do is tie the inputs together). You may ask why we'd choose to use a NAND gate as a universal gate instead of a NOR gate, the answer to this question is that it is more desirable to have NMOS transistors in series than it is to have PMOS transistors in series. NMOS transistors have a lower resistance than PMOS transistors because the electron mobility is lower than the hole mobility. This is because the electrons in the valence band are more tightly coupled to the nucleus and are harder to move than electrons in the conduction band. A CMOS NAND gate puts NMOS resistors in series and PMOS resistors in parallel, whereas a NOR gate puts PMOS resistors in series and NMOS resistors in parallel. 

AND gate:

OR gate:

NOR gate:

Then I created the 8-bit arrays for each gate:
AND:


OR:


NOR:


NAND:


NOT:


Finally, I simulated the arrays:


All of the designs work! As per the previous lab, we could utilize buffers in order to elimiate the glitches. Again, I will leave this as an exercise for the reader.

Continuing on with the experiments, I designed a 2-to-1 DEMUX/MUX and simulated its operation. First I created the schematic:

Then a symbol:

and simulated my design:


If we use the design as a MUX, when S is high Z will follow the input at A and when S is low Z will follow the input B.
If we use the design as a DEMUX, when S is high Z will propogate to A and when S is low Z will propogate to B.

Then I created an 8-bit wide 2-to-1 DEMUX/MUX. I started this design off with a schematic:

Then I created a symbol:

and finally I simulated my design:



The last experiment involved creating a full-adder by following a design in the book. I started by creating schematic:

Next, I created a symbol for the schematic:

Then, I created a layout:

Of course, we gotta extract the layout and LVS/DRC (AWWW YEAH!!!!):

(Look at all those beautiful MOSFETS!)

DRC:


LVS:


Now, it's time to design the 8-bit full-adder. Starting from the schematic:

I created a symbol view and just reused the same symbol that we created for the 1-bit full-adder but changed the inputs and outputs and tacked on "x8." I know, I know. Very Crafty.

Layout:

(Arranged vertically for the viewing pleasure of anybody who is forced to see it)

DRC:


LVS:


Simulation time:

In this simulation, we're adding 11000000 (A) and 10000100 (B). We expect to get the value 00100100 as our sum. Let's see if we do!

Eeyup, S<3> and S<6> are 1 and the other bits are zero. This is exactly what we expected!


Conclusions...
This lab expanded on the idea of the versatility of the NAND gate that we saw in the previous lab. We were able to create any gate that we wanted from just a NAND gate. We also learned how to design a MUX/DEMUX and utilize it as both a MUX and a DEMUX. Finally, we designed an 8-bit full-adder by starting with the full-adder topology that was given in the book. I feel as if this lab was a valuable learning experience and my knowledge of digital logic design was greatly heightened by it.