Lab 6: Design, Layout, and Simulation of NAND Gate, XOR Gate, and Full-Adder

By Bryan Callaway- Email: callab2@unlv.nevada.edu

Last edited: 10/20/2020

Lab description: In this lab we covered the design, layout, and simulation of a NAND gate, XOR gate, and Full-Adder in the C5 process.

In the prelab, we designed a NAND gate in the C5 process and performed a simulation:


LVS param:

After fixing things:


Lab:
NAND Gate Design:
I started the design by creating a schematic for the NAND gate:


Next, I created a symbol view:


After this, I made the layout for the NAND gate (and extracted it):

LVS/DRC:


(I decided to adjust the NAND later! This was done so it would match the height of my XOR gate layout for the full-adder design)


Simulation and truth table:


There are minor "glitches" in these results (look at the spikes in the output /out). They occur because the delays in the timing are not balanced. This problem could easily be rectified with a buffer. We can make a simple buffer by connecting two inverters together: the output of one inverter going into the input of the next. This is left as an exercise for the reader.

First, I created a schematic:

Next, I created a symbol view:

Then I made the layout/extracted the design:

Simulation of XOR gate:

Full-Adder Design:
Alright, now here comes the moment we've all been waiting for. Taking the designs of our NAND and XOR gates and using them to make one bad and wicked full-adder of truly epic proportions. I started this mean daddy-o off by creating a schematic:

Next, I created a symbol view:

Rockin!!!!!

After this, I used the layouts for my XOR and NAND gates in order to create a layout:


Look at this absolute behemoth! 

LVS/DRC:


Simulation/Truth table:

Each input is set at a different period...


Oh yeah, look at that MS Paint prowess... I should include this on my resume!