Lab 5: Design, Layout, and Simulation of CMOS Inverter 

EE 421L Digital Integrated Circuit Design

By Bryan Callaway- Email: callab2@unlv.nevada.edu

Last edited: 9/30/2020

Lab description: in this lab, we covered the creation of CMOS inverters. We designed schematics for two CMOS inverters which varied in width and length, created symbols for these inverters, and simulated our design.

The first type of inverter that I designed was a 12u (PMOS)/6u (NMOS) inverter. I started the design process by drafting a schematic:

Then I created a symbolic view for my schematic:

Then I created a layout and extracted my design:

Next, I used LVS and DRC to check my design:

And finally, I simulated the operation of my inverter for various capacitive loads. I opted to define my capacitance as a variable and use parametric analysis:

From the simulation results, it is clear that when our input is "Low" our output is "High" and when our input is "High" our output is "Low". We can also see that for large capacitance loads, the rise/fall time is slower. 

Utilizing Ultrasim:

Design of 48u/24u Inverter:

When designing the 48u/24u Inverter, I started by drafting a schematic. I reused the schematic for my 12u/6u inverter and just changed the multiplier values:

Then, I created a symbolic view:

Next, I designed a layout and extracted my design:

After this, I utilized DRC and LVS to check my design:

Finally, I simulated my design. Again, I opted to utilize a variable value for the load capacitor:


We perform parametric analysis with C as a variable:

Here we can see the value of our output for various choices of capacitance value for the load capacitor:

From the simulation results, it is clear that when our input is "Low" our output is "High" and when our input is "High" our output is "Low". We can also see that for large capacitance loads, the rise/fall time is faster.

Repeating the simulation with Ultrasim: