Lab 2: Design of a 10-bit DAC 

EE 421L Digital Integrated Circuit Design

By Bryan Callaway- Email: callab2@unlv.nevada.edu

Last edited: 9/8/2020

Lab description: In this lab we learned a large amount of information about the working principles and design of digital-to-analog converters (DAC). We designed a 10-bit DAC using resistors and simulated this design. 

Prelab:

In the prelab, we unzipped a file into the CMOSedu directory and then modified the cds.lib file in the directory so we could access the contents of this file in Cadence. This file contained many DAC and ADC design examples. We viewed and simulated the sim_Ideal_ADC_DAC design.

Simulation:

We know that for an ADC, the resolution/step size is calculated as: 

Resolution = Vout/2^N

and Vin  is converted to a digital value by dividing it by the step size. Thus, our resolution should be 5V/2^10 = 4.88 mV.

(2.50488V - 2.5V = 4.88 mV)

It is clear that our LSB = 4.88 mV

Our range is 0 - 4.995

Lab:
In this lab, we designed a 10-bit DAC based on the topology provided to us in Dr. Baker's CMOS book.

We started by designing the resistor network and creating a symbol so we could utilize it as a building block:

We can use this building block to create our DAC:

The resistance of the output of the DAC (in this case, 10k 

We can determine this by examining our resistive networks and combining series and parallel resistances. We see that the resistance of b0 is R (10k ohms) because 2R || 2R = R. Thus, b1 will have a value of R at the bottom, which implies that the reisstance of b1 is R. We can repeat this process for each network and we will see that when all resistances are combined, the resistance of the output of the DAC will be R (10k Ohms).

Generating a Symbol:
We can simply copy the provided symbolic view for the ideal_10-bit_DAC and modify it for our purposes. All we have to do it copy the symbol to the same area as our schematic design for the DAC (shown above):


Delay:
We know that Vout = Vin(1-e^-T/RC) and if we want to find Vout/2, T = td = 0.7RC. In our case, 

Which we can see is close to half of the maximum output of 1V.

Simulations:
The schematic for my ADC/DAC design can be seen below

After forcing the simulation to converge, we get these results

If we place a resistive load of 10k Ohms on the output, we get the following simulation results:


The output voltage is halved, which implies that the whole ADC-DAC circuit has an equivalent resistance of 10k Ohms.
With a capacitive load of 10pF, we get these simulation results:


We can see that the output is much smoother but there is a delay.
With an RC load, we get the following output:


With an RC load, we get half of the original signal due to our voltage division and a delay caused by the RC time constant.

Conclusions:
This lab taught me a large amount of information about the design of a DAC. I learned about calculating the LSB, range, and the effects of various load types on the output of the DAC. With regards to transistors being utilized as switches in a real ADC-DAC circuit, if the resistance of the MOSFETs are not small compared to R, they will parasitically contribute to the output resistance for DAC.