Lab 3: Layout of 10-bit DAC
EE 421L Digital Integrated Circuit Design
By Bryan Callaway- Email: callab2@unlv.nevada.edu
Last edited: 9/12/2020
Lab
description: In this lab, we created a layout for the DAC we designed
in lab 2. We did this by first using the n-well to layout a 10k Ohm
resistor and then incorporating this n-well resistor into our DAC
design.
Creation of the 10k Ohm n-well Resistor:
We
want a resistor with a value of 10k Ohms. We know that the sheet
resistance is around 800 Ohms/square and that the minimum width for the
n-well is 3.6μm. Thus, 10k = 800 * (L/3.6μm), which implies that L = 45μm. Therefore, we can create the layout for our resistor with a length of 45μm and a width of 3.6μm.
When we DRC this, we get the following:
Measuring Width and Length:
In
order to measue the width and length of our resistor, we can create
ruler by either using the bindkey k or going to Tools -> Create
Ruler.
If we want to get rid of a ruler we can hit shift-k. Let's do that and then finish creating our resistor.
We've
added connections to our resistor, now let's position them and change
our Display Level stop to 10 so we can see the outlines of the n-tap.
We can find our display level settings by pressing e.
Now
let's add pins. Go to Create -> Pin and make sure that Display
Terminal Name is checked and the material choice is metal1. We'll draw
our pins over the n-tap connectors and call our left pin L and our
right pin R.
Now we will set the resistance with the res_id layer and DRC our design
If we extract our design we get the following:
A resistance value of 10.24k Ohms, which is very close to the 10k Ohms value which we required. Good enough for government work!
Implementing our Design with the n-well Resistor:
We can create a layout view for 2R_R with our designed 10k Ohm n-well resistor.
DRC results:
LVS results:
Now we can use this layout view of 2R_R to create a layout view for our 10-bit DAC:
DRC results:
LVS results:
My Design Files Can Be Found Here
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