Lab 7 - EE 421 Digital Integrated Circuit Design 

Authored by Moriah Wingrove

Email: wingrove@unlv.nevada.edu

Due: Nov 6 2019

Prelab:

All coursework was zipped up and backed up 

Tutorial 5 was completed:

LABWORK:

The circuit for inverting a 4-bit word was created using 6u/0.6u NMOS and PMOS devices

Instead of using four inverters the schematic was condensed so only one inverter was used.The inveter was named using an array and a bus was used for the connections.

Symbol of 4-bit inverter

Schematic used for simulation

Spectre Simulation

The out<0> is inverted from the input. It has no capacitive load has the same delay, rise and fall times as the input. 

As the capacitive load increases so does the rise and fall times of the output.

Schematics and symbols for 8-bit input/output array

NAND:

NOR:

8bit symbol

AND:

schemctic and symbol of and gate

8bit schematic and symbol

Schematic used for simulating   

simulation results

Inverter:

schematic used for simulating 8bit inverter

Simulation results

OR:

2-to-1 MUX/DEMUX

schematic of MUX and symbol

schematic used for simulating MUX and DEMUX

simulation results of MUX/DEMUX  

For the MUX the output Z follows A when S is high and when S is low the output Z follows input B. When using the DEMUX the output C is the input Y when S is high and the output D is the input Y when S is low.

8bit MUX and symbol

Schematic used for simulating 8bit MUX

Simulation results of 8bit MUX

Full Adder:

Schematic of Full-Adder

symbol of full adder

Layout DRC

Layout LVS

Schematic for 8bit full adder

Symbol for 8bit full adder

Schematic used for simulating two 8bit numbers

DRC

LVS and netlist 

Return to the LABS:

Return to EE 421 Labs