Lab 6 - EE 421 Digital Integrated Circuit Design
schematic of nand gate
symbol for nand gate
Layout of nand gate
DRC clean
LVS good and netlists match
Schematic, Symbol, Layout, and Simulation of 2-input NAND gate using 6u/0.6u MOSFETS (PMOS and NMOS)
A symbol of the 2-input NAND gate was created from the schematic
A layout of the NAND gate was created using the layouts of a two PMOS and two NMOS MOSFETS. The layout was created using standard cell frames to route vdd! and gnd!. All inputs, outputs, vdd! and gnd! are routed using metal1.
DRC
LVS
Spectre Simulation
The following schematic was used to simulate the two input pulses A and B into the NAND gate as well as the output
Truth table for 2-input NAND gate
| A | B | AnandB - output |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Simulation Results
Schematic, Symbol, Layout, and Simulation of 2-input XOR gate using 6u/0.6u MOSFETS (PMOS and NMOS)
Schematic for 2-input XOR gate
A symbol of the 2-input XOR gate was created from the schematic
Layout
Layout of top half of 2-input XOR
Layout of bottom half of 2-input XOR
DRC
LVS
Spectre Simulation
The following schematic was used to simulate the two input pulses A and B into the XOR gate as well as the output simulation
Truth table for a 2-input XOR gate
| A | B | AxorB - output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Schematic, Symbol, Layout, and Simulation of Full-Adder using 6u/0.6u MOSFETS (PMOS and NMOS)
The schematic of the full-adder was created using the previous schematics and symbol views of the XOR and NAND gates.
A symbol of the full-adder was created using the above schematic
Layout
DRC
LVS
SPECTRE SIMULATION
schematic used for simulating the full-adder
Truth table for full-adder
| A | B | C | S | Cout |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
