Lab Five

Lab 421 - Digital Integrated Circuit Design

Authored by Moriah Wingrove

Due: September 25 2019

Lab Five Description:

Prelab Five:

All files were backed up and emailed to self

Tutorial 3 was then completed. A layout of the CMOS inverter was created and checked to ensure it met all the design rules. A LVS was then completed to ensure that the layout matched the schematic.

A symbol was created for the above schematic. The inverter was simulated for vdd = 5V and the input voltage V0 varying from 0 to 5V in 1mV increments

Labwork:

Experiment 1: Schematic, symbol, layout, and simulations of a 12u/6u inverter

The 12u/6u inverter was created using a 12u/0.6u pmos and 6u/0.6u nmos.

Schematic of 12u/6u inverter with input pin A and output pin Ai

a symbol of the schematic was then created

Layout of 12u/6u inverter with pins A and Ai

DRC the layout

LVS layout and show matching netlist

Schematic used for simulation

In order to save time a variable called cap was used for the capacitor and the simulation was performed using parametric analysis with the capacitor size being 100fF,1pF, 10pF,and 100pF.

Simulation results using spectre

The simulation was done again using ultrasim

Simulation results using ultrasim

The simulation results for the 12u/6u inverter look very similar. In the simulation for both the input goes from 0V to 5V. The output for each of the capacitor values is inverted meaning the output goes from 5V to 0V.

Experiment 2: Schematic, symbol, layout, and simulations of a 48u/24u inverter

The 48u/24u inverter was created using a 48u/0.6u pmos and 24u/0.6u nmos using multiplier (m=4).

Schematic of 48u/24u inverter with input pin A and output pin Ai