Lab 421 - Digital Integrated Circuit Design

Authored by Moriah Wingrove

Email: wingrove@unlv.nevada.edu  

Due: September 25 2019

Lab Four Description: 

Prelab Four:

All work for the lab and course was backed up and emailed

Tutorial_2 was then completed 


 
LABWORK:

The first part of the lab was to generate four schematics and the simulations for each schematic.

Schematic One:  A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.

   The schematic for 6u/600n NMOS 

   

VGS varies from 0 to 5V in 1V increments

VDS varies from 0 to 5V in 1mV increments

Simulation of ID v. VDS



Schematic Two:  A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.


   The schematic for 6u/600n NMOS with VDS = 100mV

 

 

Simulation of ID v. VGS

 

Schematic Three: A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio. 

The schematic for 12u/600n PMOS with varying VSD

VSG varies from 0 to 5V in 1V increments

VSG varies from 0 to 5V in 1mV increments

simulation of  ID v. VSD

Schematic Four: A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.

The schematic for 12u/600n PMOS with VSD = 100mV

VSG varies from 0 to 2V in 1mV increments

simulation of  ID v. VSG

The lab next required a lay out of a 6u/0.6u NMOS device with all 4 MOSFET terminals connected to probe pads.

A zoomed in view of the NMOS is below along with DRC results

     

The schematic for the NMOS with probe pads

       

The lab next required a lay out of a 12u/0.6u PMOS device with all 4 MOSFET terminals connected to probe pads.

The schematic for the PMOS with probe pads

The layout for the PMOS with 4 MOSFET terminals connected to probe pads

           

     


All files were backed up.

Return to EE 421 Labs