Lab 3 - EE 421 Digital Integrated Circuit Design

Authored by Moriah Wingrove

Email: wingrove@unlv.nevada.edu  

Lab description

Prelab Three:

All course work was backed up and emailed to myself. After the backup was completed tutorial one was finished. 

Extracted value of resistor R = 10.26k

LABWORK:

Using the n-well resistor made from tutorial one which has measured value of 10.26k. The length and width of the resistor was found using 

R = (p/t) *(L/W) where R is the amount of resistance, p/t is the sheet resistivity, L is the length, and W is the width. The sheet resistivity is given as 819Ω/square. 

The width of the resistor was 4.5um, using R = (p/t) *(L/W) the length of the resistor was calculated to be 56.4um.

                                                R/(p/t) = (L/W)

                                               W*R/(p/t) = L

                                               (4.5um*10.26)/819 = L

                                                   56.37um= L

The actual length of the n-well resistor is different than the calculated length due to the rectangle not being on the grid and DRC requirments.

The 10k n-well resistors were used to make a layout of the DAC from lab 2. Each n-well resistor was placed in parallel and connected together using metal 1. The input/output pins were also placed on metal 1. The layout was then verified using DRC and LVS against the schematic. 

The two images below are of the DAC layout using 10k n-well resistors that have been stacked together. The first is the entire layout and the second is a close up view of the layout.

After the layout was verified using DRC the layout was extracted. 

The extracted layout was then compared to the schematic using LVS

All lab work was then backed up

Lab_3_directory

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