Lab 1 - EE 421L 
Layout and simulation of a resistive voltage divider

Authored by Steve Salazar,

salazs3@unlv.nevada.edu

September 4th, 2019

Lab description

In this lab, we learned the basics of generating html lab reports, and we used this knowledge to create a transient analysis and simulation of a resistive voltage divider using Cadence's Virtuoso. 

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Undergoing Lab

Utilizing MobaXterm, I logged into the UNLV Cadence servers using the "ssh -X" command (forwarding) from my home computer. Then, I set up my correct VNC server address by utilizing the "vncserver -geometry "1900x1080" command in MobaXterm.

 



Utilizing the terminal window of my VNC Viewer, in conjunction with my UNLV VPN connection, (since I am working on my lab reports from home) I changed my directory to "cd $HOME" and concurrently to "cd CMOSedu". Then, I started Cadence Virtuoso using the comannd "virtuoso &" after configuring my directories.






This shows I created a new library named "Tutorial_1" and a new cell called "R_divz" in Cadence.





This shows I verified in my cds.lib file that our correct definition line was created for our new library "Tutorial_1" 



This is the schematic for our voltage divider using Cadence Virtuoso.


This verifies I used Cadence's Virtuoso Analog Design Environment (ADE) and set up Spectre simulation for my "in" and "out" signals of my voltage divider.




Using transient analysis, we obtain the graph results of our "in" and "out" signals as shown below.

In order to ensure the proper back-up of my files while building my .html lab 1 file, I made sure to create a zip file of my lab 1 folder.

After creating my zip file, I uploaded this zip file into my dedicated Dropbox network folder. This ensures all of my work does not get lost when trying to upload to the internet.

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