Project - EE 421L 

Authored by Shaquille Regis

Email: regis@unlv.nevada.edu

Part 1: November 13, 2019 - Schematic and Simulation

Part 2: November 20, 2019 - Layout, DRC and LVS

Project description:

Design x4 clock multiplier. This circuit will take a 9-11 MHz clock signal and generate a 36-44 clock signal. The input clock

is multiplied by 4 and output. Assume the input clock signal has a 50% duty cycle.

Clcok Buffer:

In order to create a multiplied clock signal, we need to create a buffered signal with sufficent delay. This can be achieved

by using inverters. The buffer comprises three stages. The first stage contains an array of 3 inverters with a width ratio of

12u/6u and length of 6u. The second stage contains two inverters with a width ratio of 12u/6u and length 6u. The final inverter

has a width ratio of 6u/6u and length of 600n.

The delay provided by this schematic was simulated to be about 26ns.

A second clock buffer was also designed for the second stage. The width ratios for all three stages remains the same. The lengths

of the MOSFET's are decreased at the second stage: 3u/6u length at the first stage (x1/x2) and 6u length at the second stage (x2).

This is to provide half of the delay time of the first clock buffer for the second stage of the clock multiplier. The delay for this

clock buffer was simulated to be about 16ns. Verification of the delays calculated for both clock buffers can be seen below in the clock

multiplier simulations.

3u length Inverter                                    6u Length Inverter                                12u Length Inverter

XOR Gate:

The XOR gate will provide the correct switching logic for a multiplied signal. To do so, the XOR gate will take the input clock

signal as is and buffered using a clock buffer as input. The XOR gate uses NMOS and PMOS of length 6u and width 600n. The

symbol view can be seen in the clock multiplier schematic.

Clock Multiplier

The clock buffer was designed with 10MHz in mind as to take into account potential swings in the input frequency. The schematic was simulated

using 9-11MHz with VDD = {4,5,6}V. As previously mentioned, the first clock buffer provides about 26ns of delay and the second clock buffer

provides about 16ns of delay.

Schematic

Symbol View

Simulation Results (x = VDD, y = frequency)

	4V	5V	6V
9MHz
10MHz
11MHz

Layout

In order to avoid a long layout, the second stage of the clock multiplier was layed out directly below the first stage

rotated 180° . This placement places ground (bodies of the NMOS) in the center of the layout.

Extracted View

DRC                                                                                                            

LVS

All cells seen in this report can be found here.

As always, remember to backup all lab materials to zip folders and email.

End of Report

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