Lab 5 - EE 421L 

Authored by Shaquille Regis

Email: regis@unlv.nevada.edu

October 9, 2019

Lab description:

This lab will go over desing and simulating CMOS inverters using MOSFET's.

Pre-lab Work:

1) Go through Tutorial 3. Tutorial 3 goes over the schematic, symbol view, layout and simulation of an inverter.

Lab Work:

1) Draft schematics, layouts and symbols for two inverters having sizes of:

    - 12u/6u (Left)

    - 48u/24u where the devices use a multiplier M = 4 (Right)

    - Note the ratios listed above represent width of the PMOS/width of the NMOS.

Schematics

Layout/Extracted

DRC/LVS

Symbol Views

2) Using SPICE simulate the operation of both inverters showing each driving a 100fF, 1pF, 10pF, 100pF capacitive load.

For simulation, the load capacitance C0 was parameterized with the variable cap. Using the Parametric

analysis in the Tools menu, cap was swept from 100f to 100p by 1 step per decade to acheive the required cacitive loads.

In adition to using Spectre as the SPICE simulator, we will be using UltraSim to simulate the inverters. UltraSim is

Cadence's fast SPICE simulator for larger circuits at a cost of accuracy. To do so, we must go to Setup -> Simulator/Director/Host

then select UltraSim. Note that in changing the simulator, we must reload the MOSFET models into ADE.

12u/6u

Spectre Simulation

Ultrasim Simulation

48u/24u

Spectre Simulation

Ultrasim Simulation

As always, remember to backup all lab work to zip folders and email.

End of Report

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