Lab 3 - EE 421L 

Authored by Shaquille Regis

Email: regis@unlv.nevada.edu

September 18, 2019 

Lab description:

Continuing from Lab 2, we will be designing the layout for the 10-bit DAC and verify the design

with Design Rule Check (DRC) and Layout Versus Schematic (LVS).

Pre-lab Work:

To prepare for the lab, complete Tutorial 1 from where we left off from Lab 1. The remainder of Tutorial 1 comprises

creating the symbol view for R_div, creating the layout for a 10k resistor and finally creating and verifying the layout

for R_div. The lab procedure will explain in detail the layout for a 10k resistor.

Lab procedure:

1) Using the 10k resitor layout created in Tutorial 1, create the layout for the 10-Bit DAC. The resistor layout consists of

    an N-well layer with n-tap contacts on either side of the N-well drawn with the res_id layer to identify that the layout

    will be a resistor.

In the C5 process, the N-well has a sheet resistance of about 800 ohms. The minimum width of an n-well is 3.6 micron. For

our purposes, the n-well for a 10k resistor has a width of 4.5 micron. From these numbers, the length of the resistor was calculated to be

56 micron. However upon DRC the length was found to be not on grid so this was adjusted to 56.1 micron and had zero errors upon

DRC. The extracted view led to a resistance of around 10.21k.

Below is the full layout of the 10-bit DAC.

A close up view of input B9 and output Vout.

All resistors are "stacked in parallel," or in other words laid out with the same X position but varying Y positions on the grid. From the design rules, each resistor has a

space of 13.5 micron in between the next resistor. All connections between resistors as well as the pins are drawn on the metal1 layer.

2) Check and save, ensure there are no DRC violations and extract the layout for LVS. All of these operations can be found under the "Verify" tab at the top

    of the Layout window.

Verify Tab

DRC

Extracted View

LVS (Note: For LVS, we will be comparing the extracted layout versus the schematic.

LVS Confirmation: LVS is successful when the netlists match. A pop up window will indicate whether or not LVS was successful.

                            You can double check by opening the output window from the LVS window shown above by pressing "Output."

As always, remember to backup your lab materials to a zip file and email to yourself.

End of Report

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