Lab 2 - EE 421L
Note: Remember to add a DEFINE statement to uploaded directories in the cds.lib file.
Below is the schematic for simulation. The schematic consists of an AC voltage source at the input of the Analog-
to-Digital Converter (ADC). The ADC converts the input source voltage into a digital binary value of 1 or 0
outputting via B[9:0]. B[9:0] represents a 10-bit binary value that is input into the Digital-to-Analog Converter
(DAC). The DAC converts this 10-bit binary value into a voltage at node Vout. Each bit correlates to a multiple of
1 LSB, which is 4.88mV from this simulation as shown below.
Open ADE L, load the simulation state and run the simulation.
Lab Procedure:
1) Copy the ideal_10-bit_DAC cell and rename it. I will be renaming it my_10-bit_DAC.
2) Open the schematic for My_10-bit_DAC and build the following schematic. The schematic utilizes 10k resistors.
Be sure to check and save and verify no errors are present.
The Resistance of the DAC can be calculated by combining the resistors that are in series and parallel.
Below is an example of combining resistors in a 3-bit DAC.
3) Ground all input pins except B9 of the DAC and calculate the td. When driving a load of C = 10pF, td was found to be
about 70ns.
Hand Calc here
4) Create a new symbol view for the 10-bit DAC. This can be done by going to Create -> Cellview -> From Cellview then press
OK.
The Schematic below was used for step 3 in this report.
5) Copy the sim_Ideal_ADC_DAC cell to a new cell titled sim2_Ideal_ADC_DAC. Replace the Ideal DAC in the schematic with
the newly created symbol.
The simulation output is nearly identical to the orginal ideal simulation.
With a capacitance load of 10pF, there is a delay of about 70ns which corresponds to the earlier calculation of td.
With an RC load of a 10k resistor and 10pF capacitor, the output voltage is significantly attenuated, with a delay of about 47ns
between the input and output voltages.
As always, remember to backup your lab materials to a zip file and email to yourself.
End of Report