Lab 4 - EE 421L 

Authored by Cristian Ramirez,

ramirc5@unlv.nevada.edu

September 25th, 2019

Lab description

In this lab, I worked on showing I-V curves of different configurations of NMOS and PMOS transistors. 

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I worked on tutorial 2 for the EE 421 Lecture already, so the pre-lab was no problem. I had already finished the bulk of it, so I used that.

After that, I made the following schematic, set up an analysis just like in Tutorial 2, and got the following results.

For the second part, I did a similar thing except instead of setting VGS as a variable with parametric analysis, I put in more constant values and did a DC sweep.

Going over to the third experiment, I made a different schematic in order to do the experiment with a PMOS configuration. Similarly with the first experiment, I shadowed Tutorial 2 to set up an analysis to sweep two voltages, VSG and VDS.

And similarly with the second experiment, I set up a different DC sweep for only a variable VSG.

Unfortuantely, I was only able to go so far with the fifth experiment before time ran out. I got up to laying out the entire NMOS, after making the bond pads and schematic + symbol.

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