Project - EE421L F19

Project - ECE 421L

Authored by Geovanni Portillo,

Date Last Modified: November 13th, 2019

Goal: Design a circuit that takes a clock signal ranging from 9-11MHz and generates a 36-44MHz clock signal; a x4 clock multipler. Assume the clock

has a duty cycle of 50%

Project Requirements:

First half of the project (schematics and design discussions) of your design and an html report detailing

operation (including simulations), is due at the beginning of lab on Nov. 13.

Your design report in html should show various input clock frequencies and VDD voltages to show it works.

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.

Dr. Baker will go over your design with you (in person), including running simulations, when lab meets on Nov. 13.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 20.

Dr. Baker will meet with you on Nov. 20 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.

Ensure that there is a link on your project report webpage to your zipped design directory.

The design directory can be downloaded as a zip file here.

Part 1 (Schematics and Design Discussions):

Design Discussion:
To generate an output clock signal that is four times faster than the base clock, the circuit below is used. The circuit will be made up of two XOR gates and two delay components.

Both XOR gates will be used to generate clock signals twice as fast as the input. This will be done by giving the same input signal to both inputs of the XOR gate while delaying one of the them.
When the input signal transitions, the inputs of the XOR gate will differ for the duration of the delay which causes the output to be high for that duration. This is visualized by the drawing below.

Given the input signal should be able to range from 9-11MHz with the circuit being capable of generating a x4 clock signal, I'm choosing to design with 10MHz in mind.
This is so that if there are variations in the design that would result in the range of frequency shifting lower or higher, it should still be closer to the desired range than if designing with the edges of 9 or 11MHz in mind.

For an input signal of 10MHz with a 50% duty cycle, the output of the first-stage XOR gate would have a frequency of 20MHz with a 50% duty cycle. The first stage delay should then be equal to half the period of the output signal, 50ns. So, the delay would be 25ns. For the second-stage XOR gate, the output will be 40MHz (T = 25ns) and so the delay will need to be about half the period, 12.5ns, to achieve a 50% duty cycle.

Component Schematics and Simulations:

The design of the XOR gate in Lab 6 will be used for both XOR gates in this circuit. The function of the XOR gate is that the output will be high when the inputs are not equal otherwise the output is low.
F = AB' + A'B.

XOR GATE
Schematic	Symbol

Simulation Schematic
Simulation Output

The delay will be implemented by using a string of inverters using the inverter components below.

Inverter 12u/6u (L = 0.6u)
Schematic	Symbol

Inverter 12u/6u (L = 6u)
Schematic	Symbol

For the first-stage inverter, to create a delay near 25ns, eight of the 6um length inverters were used with two 0.6um length inverters that are used to reduce the time the signal takes to transition.
The delay for when the input signal transitions from low-to-high is 23.8ns with the high-to-low delay being 24.3ns.

Delay Stage 1 Schematic
Simulation Schematic
Simulation Graph

Using the delay component for the first-stage, the output signal generated from the XOR gate has a period of about 50ns with a pulse width of about 23.4ns.
Or said differently, the output signal has a frequency of about 20MHz with a duty cycle of 46.8%.

Simulation Schematic
Simulation Graph

To create a delay of about 12.5ns for the second-stage delay, four of the 6um length inverters were used with two 0.6um length inverters.
The low-to-high delay is 13ns and the high-to-low delay is 14ns.

Delay Stage 2 Schematic
Delay Simulation Schematic
Delay Simulation Graph

Final Circuit Schematic and Simulations:

Using both delay components, the x4 clock is implemented and simulated below.

For the simulations, the input will have a 5V amplitude with varying frequencies and VDD voltages.

As VDD increases, the pulse width decreases and vice versa while the peak voltage will be about the same as VDD.

As the frequency decreases, the pulses became more offset towards the start of the low-to-high transition.

And as the frequency increases, the pulses became more offset towards the start of the high-to-low transition.

x4 Clock
Schematic
Simulation Schematic

F = 9MHz VDD = 4V
F = 10MHz VDD = 4V
F = 11MHz VDD = 4V
F = 9MHz VDD = 5V
F = 10MHz VDD = 5V
F = 11MHz VDD = 5V
F = 9MHz VDD = 6V
F = 10MHz VDD = 6V
F = 11MHz VDD = 6V