Lab 2 - EE 421L 

Authored by Peter Kim

kimj98@unlv.nevada.edu

September 11th, 2019

Pre-lab:

· Back-up all of work from the lab and the course.

· Download lab2.zip and run the simulation.

(screenshot of sim_Ideal_ADC_DAC from lab2.zip)

· First you load the schematic and launch ADE L and load saved state and run the simulation

(Result)

Determine the least significant bit (LSB) using following equation.

Lab:

· Use n-well resistors to implement a 10-bit DAC by using Fig. 30.14 in the CMOS book.

· First step is you open up a new schematic and draw the 10-bit version of figure 30.14.

· Check and save the schematic, make sure there is no warning or error.

· At this point, you could have performed the simple simulation of adding a source and a load

but, creating a symbol view for the schematic is easier to make modification.

· To create a symbol, Select, Create -> Cellview -> From Cellview…

(make backup copies for modifications)

(add a source and a 10pF load for testing the 10_bit_DAC, check and save the file, run ADE L and run simulation)

Predict by using 0.7RC = (0.7)(10k)(10pF) = 70ns

Open the lab2_sim_Ideal_ADC_DAC and delete the existing 10-bit DAC and replace it with the new one called 10_bit_DAC.

Run simulation and compare the result with one in the pre-lab.

Once we have verified that the new 10-bit DAC is working, add a Resistor load, a capacitor load, and add both load at the same time

- Added a resistor load

Result

-Added a capacitor load

-Result

-Added both loads

-Result

Return to EE 421L Labs