Project - EE 421L
Authored
by Cody Jones,
E-mail:
Jonesc30@unlv.nevada.edu
11/6/18
Project: Design a circuit that takes a 9-11 MHz clock signal and generates a 36-44 MHz clock signal. In other words, design x4 clock multiplier. The input clock is multiplied by 4 and output. Assume the input clock signal has a 50% duty cycle.
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Schematics and design discussions:
Inverter
12u/6u
Used
to square up the signal from the long length inverters.
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Schematic |
Symbol |
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Inverter:
PMOS-12u/12u and NMOS-6u/12u
Used
to add delay to our signal. I use it in my 25ns delay device and my 12.5ns
delay device.
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Schematic |
Symbol |
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XOR
The
XOR is used so that the when the original signal is XOR’d
with the delayed signal, it will be an edge detector. This means when original
signal goes high the output of the XOR will go high while the delayed signal is
still low. When the delayed signal finally goes high the output will be zero.
The XOR function is F = A’B + AB’.
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Schematic |
Symbol |
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My
25ns delay device
The
25ns delay device is used to delay the input signal. I have chosen the delay to
be 25ns because our frequency is 9-11MHz. This will give a period of around
100ns. With a 25ns delay, it will cause two 25ns pulse widths within the 100ns
period once it goes into the XOR, thus giving two periods of 50ns with a duty
cycle of 50% (doubling the frequency). Since I am using two inverters for the
project and want to be optimal, the closest delay I could get is roughly 23ns.
The input signal goes into a string of long length inverters and then are
squared up by a string of the smaller length inverters.
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Schematic |
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Simulation
Schematic |
Simulation
Results |
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Looking
at the simulation results, the input signal was Wi<1> and Ei<2> is the output from the long length inverters.
However, I used 3 inverters to get 23ns, so I needed to square it up and invert
the signal which ended up giving me the result of Ri<2> as my final result.
My
12.5ns delay device
The
12.5ns delay device is used to delay the signal that was doubled in frequency.
The 12.5ns delay was chosen because the double frequency from the first XOR has
a period of roughly 50ns. I played the same game as the 25ns delay device, so
the 12.5ns delay device XOR’d with the doubled
frequency will cause a final output of 25ns period where is this 4 times faster
than our original. My delay is roughly 10ns, but the ideal delay device would
have been 12.5ns. I only wanted to use two types of inverters and as few as I
could.
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Schematic |
Symbol |
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Simulation
Schematic |
Simulation
Results |
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In
the simulation results, we can see that P is the input and Qi<1> is the
output through the long length inverters and need to be squared up. This gives
us the final product of Mi<1>
My
x4 clock multiplier
The
x4 clock multiplier takes an input signal that runs into an XOR where the other
terminal is the same signal but with a delay. That doubled frequency signal
does the same thing and will give us an output that is now four times the input
frequency. I added a series of two inverters on the final result because it was
taking 1 ns to rise and caused one of my simulations to not work properly.
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Schematic |
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Simulation
Schematic |
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Results:
10MHz and VDD at 5V |
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Results:
11 MHz and VDD at 6V |
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Results:
9MHz and VDD at 3.5V |
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Speeding
up the frequency and increasing VDD causes the x4 signal to increase in amplitude
and narrow the periods. Lowering the frequency and lowering VDD causes the x4
signal to decrease in amplitude and increase the period length.
Layouts
Components
of the devices
All
these components have been DRC and LVS through previous assignments.
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Layout |
Extracted |
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12u/6u inverter |
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12u/6u (L=12u) inverter |
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XOR |
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Layout
of 25ns delay device
Layout
of the 3 long length inverters and 3 short length inverters where their output
is combined into the input of the next inverter. All the vdd!
and gnd! are connected to an inputoutput
terminal for the device. There is also an input terminal in and an output
terminal out.
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Layout |
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Extracted |
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DRC and LVS |
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Layout
of 10ns delay device
Layout
with the 2 long length inverters and 2 short length inverters. It is connected similar to the layout of the 25ns delay device.
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Layout |
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Extracted |
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DRC and LVS |
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Layout
of x4 clock multiplier
There
is an input terminal that is connected to both the 25ns delay device and to the
XOR input B. The 25ns delay device output is connected to A. The output of the XOR,
AxorB, is connected to the second XOR input A and the
10ns delay device is connected to the XOR input terminal B. The output of the
second XOR, AxorB, goes into the two short inverters
where the output terminal out can be found. All vdd! are
connected to each other for one vdd! inputoutput terminal and as well as for all gnd! being connected to one gnd!
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Layout |
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Extracted |
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DRC and LVS |
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All
LVS were ran with the FET parameters to check for sizes as well.
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Link to my zipped project directory.
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This
Concludes the Project Report.