Lab 07 - EE 421L
Authored
by Cody Jones,
E-mail:
Jonesc30@unlv.nevada.edu
10/31/19
Lab 07: Using buses and arrays in the design of word inverters,
muxes, and high–speed adders.
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Prelab: Insight on using arrays, buses and
how to make a ring oscillator.
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Concise
ring oscillator |
Simulation |
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Layout |
Extracted |
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LVS |
DRC |
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Lab:
Step 1: Make an equivalent, more concise, schematic by instantiating an inverter and naming the inverter using an arrayed name (I0<3:0> see image below).
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6u/0.6u PMOS and NMOS inverter symbol |
Inverter
schematic |
Concise x4 inverter schematic |
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Step 2: Using this symbol create a simulation
schematic. All four inverters' inputs are tied together to an input pulse
source.
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Schematic of simulating the x4 inverter |
Graph of the simulation of the x4 inverter |
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Step 3: Create schematics and symbols for an 8-bit input/output array of: NAND, AND, NOR, OR, and inverter gates.
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Symbol |
Concise
schematic |
CMOS
schematic for one |
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NAND |
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AND |
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NOR |
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OR |
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Inverter |
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A
complete simulation of all the gates from above where the 0th bit is
taken as a test for confirmation that the gate is correct.
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Simulation
schematic |
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Simulation
results |
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Step 4: Next examine the schematic of a 2-to-1 DEMUX/MUX
(and create the symbol).
Simulate the operation of this circuit using Spectre
and explain how it works.
Make
sure to show, using simulations, how the circuit can be used for both
multiplexing and de-multiplexing.
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2-to-1 DEMUX/MUX schematic |
2-to-1 DEMUX/MUX symbol |
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Simulation schematic |
Simulation graph |
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We
can see that when S is 0, we get the signal B and then when S switches to 1, we
get the signal of A. This gives the equation where Z = A*S + B*Si. This is
because S is selecting what signal Z will be.
Step 5: Create an 8-bit wide word 2-to-1 DEMUX/MUX
schematic and symbol.
Include an inverter in your design so the cell only needs one select input, S
(the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.
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DEMUX/MUX x8 schematic |
DEMUX/MUX x8 symbol |
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Simulation of the DEMUX x8 |
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Simulation of the MUX x8 |
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Step 6: Finally, draft the schematic of the full-adder seen in
Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
Create an adder symbol for this circuit (see the symbol used in lab6). Use
this symbol to draft an 8-bit adder schematic and symbol.
For how to label the bus so the carry out of one full-adder goes to the carry
in of another full-adder review the ring oscillator schematic discussed in
Cadence Tutorial 5. Simulate the operation of your 8-bit
adder. Lay out this 8-bit adder cell. Show that
your layout DRCs and LVSs correctly.
Full
adder schematic
Full
adder layout
Full
adder extracted
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Full adder symbol |
LVS and DRC |
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Full adder x8 schematic |
Full adder x8 symbol |
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Full adder x8 layout |
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Full adder x8 extracted |
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A
close up of the connections between full adders
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LVS and DRC |
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Simulation of the full
adder x8 |
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Looking at just the eighth bits, we can see that when we have A<7> and B<7> both as one we get a carry out and that the eighth bit of our sum is correct.
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This
Concludes the Lab 7 Report.