Lab 05 - EE 421L
Authored
by Cody Jones,
E-mail:
Jonesc30@unlv.nevada.edu
10/6/18
Lab 05: Design, layout, and simulation of a CMOS inverter.
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Prelab:
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Schematic
of CMOS inverter |
Symbol
of CMOS inverter |
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Layout
of CMOS inverter |
Extract
of CMOS inverter |
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LVS
approved |
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Sim of
CMOS inverter |
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Lab:
Step
1: Drafting
the layout and schematic for 12u/6u CMOS inverter.
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12u/6u
CMOS inverter schematic |
12u/6u
CMOS inverter symbol |
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12u/6u
CMOS inverter layout |
12u/6u
CMOS inverter extracted |
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12u/6u
inverter LVS approved |
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DRC
approved |
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Step 2: Drafting the layout and schematic for 48u/24u CMOS
inverter. (I made the mistake of calling my cell files 48u_12u instead of 48u_24u)
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48u/24u
CMOS inverter schematic |
48u/24u
CMOS inverter symbol |
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48u/24u
CMOS inverter layout |
48u/24u
CMOS inverter extracted |
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48u/24u
inverter LVS approved |
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DRC
approved |
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Step 3: Zipped up files can be found here
Step 4: Simulations of the 12u/6u inverter with different
capacitor loads.
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12u/6u
inverter with 100fF capacitor load |
12u/6u
inverter with 1pF capacitor load |
12u/6u
inverter with 10pF capacitor load |
12u/6u
inverter with 100pF capacitor load |
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Step 5: Simulations of the 48u/24u inverter with different
capacitor loads.
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48u/24u
inverter with 100fF capacitor load |
48u/24u
inverter with 1pF capacitor load |
48u/24u
inverter with 10pF capacitor load |
48u/24u
inverter with 100pF capacitor load |
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Step 6: Comment on results from simulations.
As the load capacitance is increased, the time it takes to charge the capacitor at the output is longer in response to change in the voltage input. So, it will not charge fully in our period with a higher capacitance load. We can see that when we combine the MOSFETs in series from 12u/6u to 48u/24u that it can charge a bigger load. For example, when the 12u/6u charges a 10pF capacitor it barely makes half of the input voltage whereas the 48u/24u almost charges the 10pF capacitor fully to the input voltage before discharging.
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This
Concludes the Lab 3 Report.