Lab 03 - EE 421L
Authored
by Cody Jones,
E-mail:
Jonesc30@unlv.nevada.edu
9/15/18
Lab 03: Layout of a 10-bit DAC using the resistor from Lab
2.
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Prelab:
I
have went through tutorial 1 and here is proof with some pictures that show
that I know how to use the content from tutorial 1.
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Lab:
1:
How
to select the width and length of the resistor is by using the formula, (R/800)=(L/W). I choose my width to be 4.5um because it will snap
easily in Cadence and allows the ntaps to snap onto
the n-well. With a 4.5um, the length will be 56.1um. In Cadence, width=height
and length=width.
Once
you have the parameters for your body of the resistor, add the ntaps with pins so that the ntaps
line up with the body. Then apply the res_id layer
over the body of the resistor and extract.
The
extracted layout of the 10K resistor.
2:
Since
we are using 10k resistors for the DAC we will use the same parameters for
width and length as discussed above. It is important to space out the resistors
in the layout and to have them on x and y coordinates that are divisible by 0.15um.
The resistors are in parallel with the same x-position but varying with
y-positions. The pins and wiring are metal1.
Example
of one pin.
The
extracted layout.
The
DRC approval
The
LVS approval
To
get the final design directory for lab3.