Lab 5 - ECE 421L 

Mohammad Islam,

11/9/2019 

Email: islamm1@unlv.nevada.edu 


Lab description

12u/6u inverter schematic, layout, and symbol:


12u/6u inverter DRC:

12u/6u inverter LVS:

48u/24u inverter schematic, layout, and symbol:


48u/24u inverter DRC:

48u/24u inverter LVS:

The inverters SPICE simulates with a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load was setup with parameter sweep.


12u/6u inverter simulation result:

48u/24u inverter simulation result:

For the simulation result, the 48u/24u inverter has a faster response. This is due to having more inverter means to having a buffer that outputs strong highs and lows.

Lab5 directory

Return to EE 421L Labs