Lab 5 - ECE 421L
Mohammad Islam,
11/9/2019
Email: islamm1@unlv.nevada.edu
Lab description
12u/6u inverter schematic, layout, and symbol:
![](inverter_schematic.PNG)
![](inverter_layout.PNG)
![](inverter_symbol.PNG)
12u/6u inverter DRC:
![](inverter_DRC.PNG)
12u/6u inverter LVS:
![](inverter_LVS.PNG)
48u/24u inverter schematic, layout, and symbol:
![](inverterx4_schematic.PNG)
![](inverterx4_layout.PNG)
![](inverterx4_symbol.PNG)
48u/24u inverter DRC:
![](inverterx4_DRC.PNG)
48u/24u inverter LVS:
![](inverterx4_LVS.PNG)
The inverters SPICE simulates with a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load was setup with parameter sweep.
![](inverter_sim_sweep.PNG)
![](inverter_sim_setup.PNG)
12u/6u inverter simulation result:
![](inverter_sim.PNG)
48u/24u inverter simulation result:
![](inverterx4_sim.PNG)
For
the simulation result, the 48u/24u inverter has a faster response. This
is due to having more inverter means to having a buffer that outputs
strong highs and lows.
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