Lab 4 - ECE 421L 

Mohammad Islam,

09/25/2019 

Email: islamm1@unlv.nevada.edu

Lab description

The purpose of this lab is to learn about MOSFETS through cadence. These are the 4 schematics and simulations.

• A schematic for simulating ID v. VDS of an NMOS device.

• A schematic for simulating ID v. VGS of an NMOS device. 

• A schematic for simulating ID v. VSD of a PMOS device. 

• A schematic for simulating ID v. VSG of a PMOS device.  

The layout for a 6u/0.6u NMOS device with connection to probe pads.

DRC:

LVS:

The layout for a 12u/0.6u PMOS device with connection to probe pads.

DRC:

LVS:

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