Lab 3 - ECE 421L
Mohammad Islam,
09/18/2019
Lab description
This propose of this lab is to learn how to use cadence’s layout system
and create the layout for the DAC.
The first step was make a 10k resistor using n-well as shown below.

The table shows the sheet resistance of n-well is 855 ohm per square. This
means to get 10k resistor there need to 11.7 squares. The width of the n-well
is 4.5um, form the tutorial, therefore length has to 56um.

This image shows the complete layout of DAC

DRC:

LVS:

Lab3 directory
Return
to EE 421L Labs