Lab 2 - ECE 421L
The purpose of this lab is to create and test a schematic for a digital to analog converter. The picture below shows the schematic that I have created.
The output resistance can be calculated by finding the equivalent resistance of each section one at a time as shown in the picture.
Therefore the output resistance is 10k. This means if all DAC inputs except B9 is connected to gnd, B9 to a pulse source and the DAC is driving a 10pF load the schematic can be simplified to this image.
The delay is 0.7RC= 0.7*10k*10p= 70ns. The simulation shows that the delay is 75ns.
The symbol for my DAC:
The full circuit:
Simulation with input of sin and no load:
Simulation with input of sin and 10k load:
Simulation with input of sin and 10pF load:
Simulation with input of sin and 10k and 10pF load:
Simulation with input of ramp and no load:
Simulation with input of ramp and 10k load:
Simulation with input of ramp and 10pF load:
Simulation with input of ramp and 10k and 10pF load:
In a real circuit if the MOSFET switches' resistance is about the same as the resistor. The output resistance would incease to 1.2R