Lab 7 - ECE 421L
Connect a wide-wire (bus) as seen below and connect it to input and output pins. Create a symbol for the schematic.
4-bit Inverter Symbol:
Consise 4-bit Inverter Schematic:
Using this symbol create a simulation schematic. All four inverters' inputs are tied together to an input pulse source.-> The out<0> is not connected to a load while out<3> is connected to a 100fF load.
-> The out<1> is connected to a 1 pF load while out<2> is connected to a 500 fF load.
4-bit Inverter Simulation Schematic:
4-bit Inverter Simulation Output:
Based from the simulation output, we can see as the capacitive load increases on the output, the delay RC rise/fall increases.
This increase in time is not ideal for digital logic gates since we want our states to change from vdd to ground or ground to vdd instantaneously.
Create schematics and symbols for an 8-bit input/output array of: NAND, AND, NOR, OR, and inverter gates.
NAND:
Schematic:
8-bit Schematic:
8-bit Symbol:
AND:
Schematic:
8-bit Schematic:
8-bit Symbol:
NOR:
Schematic:
8-bit Schematic:
8-bit Symbol:
OR:
Schematic:
8-bit Schematic:
8-bit Symbol:
Inverter:
Schematic:
8-bit Schematic:
8-bit Symbol:
Provide a few simulation examples using these gates:
NAND:
8-bit Simulation Schematic:
8-bit Simulation Output:
AND:
8-bit Simulation Schematic:
8-bit Simulation Output:
NOR:
8-bit Simulation Schematic:
OR:
8-bit Simulation Schematic:
Inverter:
8-bit Simulation Schematic:
Next examine the schematic of a 2-to-1 DEMUX/MUX (and create the symbol).
Simulate the operation of this circuit using Spectre and explain how it works.
Make sure to show, using simulations, how the circuit can be used for both multiplexing and de-multiplexing.
MUX/DEMUX Schematic:
MUX/DEMUX Symbol:
Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.
8-bit MUX/DEMUX Schematic:
8-bit MUX/DEMUX Symbol:
8-bit MUX Operation Simulation Schematic:
8-bit MUX Operation Simulation Output:
8-bit DEMUX Operation Simulation Schematic:
8-bit DEMUX Operation Simulation Output:
Create an adder symbol for this circuit (see the symbol used in lab6). Use this symbol to draft an 8-bit adder schematic and symbol.
For
how to label the bus so the carry out of one full-adder goes to the
carry in of another full-adder review the ring oscillator schematic
discussed in Cadence Tutorial 5. Simulate the operation of your 8-bit adder. Lay out this 8-bit adder cell. Show that your layout DRCs and LVSs correctly.
8-bit Full Adder Schematic:
8-bit Full Adder Symbol:
8-bit Full Adder Layout:
The pins on the 8-bit layout are connected from one Cn to the next Cn pin as shown:
8-bit Full Adder Operation Simulation Schematic:
8-bit Full Adder Operation Simulation Output:
