Lab 6 - ECE 421L 

Mohammad Islam,

09/11/2019 

Email: islamm1@unlv.nevada.edu

Lab description

For the first part of the lab is creating schematics for inverter, 2-input NAND gate and 2-input XOR gate using 6u/0.6u for both NMOSs and PMOSs. Below are images of the schematics, symbols, DRC and LVS of inverter, NAND and XOR gates. 

Inverter:

DRC:

LVS:

NAND:


DRC:


LVS:

XOR:


DRC:


LVS:


Using Spectre simulate the operation of the gates were tested for the inputs AB = 00, 01, 10, 11. Below are truth tables showing the operation of the inverter, the NAND gate and XOR gate along with images of the schematic that was generated with the gates and the simulation results.

A

B

AnandB

AnandB

AxorB

0

0

1

1

0

0

1

1

1

1

1

0

0

1

1

1

1

0

0

0

As seen from the results the gates' operation match that of their respective truth table as expected. It should be noted that there is a glitch in the output for the XOR gate. This occurs due to the input A being on the rising edge and input B being on the falling edge at the same time. The XOR gate sees this as both inputs being off, or having no value, which gives a false input of 0 momentarily until both inputs go their respective vaules.  

 

For the last part of the lab is drafting a schematic and a layout of a full-adder using the created NAND gate and XOR gate. Below are the images of the full-adder schematic, symbol, layout, DRC and LVS.

 

DRC:


LVS:

The schematic was simulated using Spectre and the results were as expected with the outputs matching up with values given on the truth table. Below is the full-adder truth table, images of the schematic using the full-adder symbol and the results of the simlulation.

a

b

cin

s

cout

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1



The glitches or false outputs given for the results of the full-adder occur for the same reason given above, where two or more inputs are on the falling edge or rising edge at the same time. This results in the output viewing these as being off or having no value and giving an output that coincides with these inputs being 0. 

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