Lab Project - ECE 421L 

Lizz Heider

heider@unlv.nevada.edu

PROJECT FILES DOWNLOAD: Lab_Project.zip

OVERVIEW

The task given was to design a circuit that would take a 9 to 11MHz clock signal and increase it

from 36 Mhz to 44 Mhz clock signal.

In other words design a X4 Clock Multiplier (Quadruple the Frequency)

DESIGN ANALYSIS

THE XOR GATE

Returns true when an odd number of inputs are true. Two input XOR, will return “true” when an odd
number of inputs are “true.”

ADDING A DELAY BLOCK

We add a delay block so that the clock will be high when only one of the two out of phase clocks is high, which

happens to be twice as often as the original clock.
We then take the output of the XOR gate, plug it into another XOR gate, and then quadruple our frequency.

In design and simulation process we first test to double our frequency through one delay block and one XOR gate.

For the first delay block, we want to create a delay block for 50nS.

The second delay block we want to delay for 25nS.

Long Inverter – Schematic and Symbol

The long inverter’s main purpose is to generate a significant delay between its input and output. As we put these

in series it increases the delay.

COMPONENTS USED

Standard (Short) Inverter – Schematic and Symbol
The standard inverters create buffers within the circuit. Buffers square the output of the circuit.

Simple “baby” Buffer is just two standard inverters in series. For schematic purposes I just created a symbol.

Delay Block 1

Simulating delay block 1:

Delay Block 2

Full X4 Schematic

SIMULATIONS

5V – 9MHz

6V – 9MHz

5V – 10MHz

6V – 10MHz

LAYOUTS

Inverter- Standard

Inverter - Long

XOR Gate Layout

Below is the layout of the (dblock)

Below is the layout of the second delay block (dblock_2)

FULL LAYOUT

LVS Verification

Closer Look at Layout (Right Hand Side, Left Hand Side)

Extracted Layout