Lab 5 - EE 421L 

Authored by Adrian Angelo G Fuerte

Rebelmail: fuerta1@unlv.nevada.edu

Date: 10/09/2019

Pre-Lab

In this laboratory, the pre-lab consisted of backing up all our work from the lab and the course and going through Tutorial 3, whichconsisted of design, layout, and simulate a CMOS inverter. I started by copying the Tutorial_2 library to a library named Tutorial_3, then created a new cell view of a schematic called "inverter". Tutorial_3 covered making the schematic, symbol, and layout for the inverter and simulating it.

Inverter Schematic

Inverter Symbol

Inverter Layout

After making the layout, I had to DRC and LVS to make sure that there are no errors and to make sure that the schematic matches the layout.

DRC

LVS

The next step was to simulate the inverter as seen in Tutorial_3. After that simualtion, I added a VDD on the schematic and simulated again.

Schematic

Simulation Result

Schematic with VDD

Simuation Result (with VDD)

Lab description

Part 1: Creating the Schematic, Symbol, and Layout for 12u/0.6u PMOS and 6u/0.6u NMOS

The first step that I did is to copy my Tutorial_3 libary to a new library called "Lab_5". I then re-used my inverter schematic and changed the sizes of my NMOS and PMOS to the given sizes for this lab which was 12u/0.6u for the PMOS and 6u/0.6u for the NMOS. I then created a symbol and layout for the schematic.

NOTE: Since I have finished Tutorial_3 prior to doing the lab, I will be using my files from Tutorial_3 for the first part of this laboratory. In short, all the schematics, symbols, and layout for the first part of this lab will come from my Tutorial_3 folder.

Copying Tutorial_3 to Lab_5 library

Inverter Schematic

- The inverter that is going to be used in this lab is the same inverter used in the pre-lab (Tutorial 3).  The source of the PMOS is connected to VDD, the drain of both the PMOS and the NMOS are connected together which forms the output (Ai) of our inverter and the gates for both of the transistors connect together to form the input for our inverter (A).

Inverter Symbol (From the Schematic above, create->cell view -> from cell view)

Inverter Layout

- After doing the layout, I DRC'd and LVS'd my layout to make sure that there were no errors in the DRC and that the netlists match for the LVS

Extracted View

DRC for Layout

LVS

Part 2: Creating the Schematic, Symbol, and Layout for 12u/0.6u PMOS and 6u/0.6u NMOS with a multiplier of 4 (m=4)

The first step that I did is to copy my schematic of the inverter to a new cell called "inverter_m4" and changed the multiplier for both the PMOS and the NMOS to m=4. I then created a symbol and layout for this schematic of my inverter.

Copying inverter to inverter_m4

-To do this, right click on the schematic view from the inverter cell-->copy

- To change the multiplier from m = 1 to m = 4, click on the PMOS or NMOS and press Q then change the multiplier to m = 4 (shown in the images below)

For PMOS (m = 4)

For NMOS (m = 4)

Inverter Schematic with m = 4

Inverter Symbol m = 4

-create->cell view -> from cell view then press okay twice

Inverter Layout m = 4 and DRC

 Inverter Extracted View and LVS

Part 3: Simulations using Parametric Analysis with the cap variable

- The first thing I did is to create a new schematic for simulation purposes. I created a file called sim_inverter for my 12u/6u inverter. Then I created the schematic using my 12u/6u symbol, the following schematic is shown below. I used a voltage pulse of 0V to 5V with a rise time of 1ns, pulse width of 10ns, and a period of 20ns. The following schematic will be simulated with varying capacitive load (100fF, 1pF, 10pF, and 100pF) using parametric analysis.

Schematic (12u/6u inverter)

Object Properties for voltage pulse

Simulation Result 

- Transient of 0 to 25ns, Plotting A (input) and Ai (output), Using Parametric analysis from 100fF to 100pF

- As we can see in the graph below, the higher the capacitance is, longer the rise and fall time is going to be.

  
 Schematic (12u/6u with multiplier of m = 4)
 

 
Simulation
- With a bigger capacitor, we can see that we get a faster rise and fall time compared to the 12u/6u inverter
-The graph below shows multiple capacitance values in 1 graph.
 

 
Part 4: Simulation using UltraSim
 
Setting up UltraSim

 
UltraSim Simulation Result for 12u/6u Inverter
 

 
UltraSim Simulation Result for 12u/6u Inverter with m = 4

Files that are used in this lab can be downloaded here: Lab_5 files

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