Lab 7 - EE 421L 

Authored by Adrian Angelo G Fuerte

Rebelmail: fuerta1@unlv.nevada.edu

November 6, 2019

Pre-Lab

The pre-lab consisted of going through Tutorial 5, which was to design, layout, and simulate a ring oscillator. Below are images from Tutorial 5

Ring Oscillator Layout

Ring Oscillator Simulation Result

Ring Oscillator LVS

Lab description

Part 1

For this lab, we are tasked to make an equivalent, more consice schematic by instantiating an inverter and making that inverter an array of <3:0>

Inverter (6u/.6u for both NMOS and PMOS) Symbol

Finished Symbol

Using the inverter symbol above, I created a simulation schematic which consisted of all four inveter's input connected to a pulse voltage from 5V to 0V and simulated it.

Simulation Schematic

Simulation Result

Part 2

The second part of this lab is to create schematics and symbols for an 8bit input/output array of the following gates: AND, NAND, NOR, OR, and INVERTER

8 bit AND gate

Schematic

Symbol

Simulation Schematic and Result

8 bit NAND gate

Schematic

Symbol

Simulation Schematic and Result

8 bit NOR gate

Schematic

Symbol

Simulation Schematic and Result

8 bit OR Gate

Schematic

Symbol

Simualtion Schematic and Result

8 Bit Inverter Gate

Schematic

Symbol

Simulation Schematic and Result

Part 3: 2 to 1 MUX/DEMUX

The next step was to examine the schematic of a 2 to 1 MUX/DEMUX taht is given in the lab and its symbol. The task is to simulate the operation of this circuit using Spectre and explain its purpose/function.

Schematic

Symbol

Simulation Schematic and Result

-> As can be seen in the simulation above, for the MUX when S is "0" the output becomes B input and when S is "1" the output becomes A input. For the DEMUX, When S is "1", B takes the signal of Z and when S is "0", A takes the signal of Z.

Part 4: Creating an 8-bit 2 to 1 MUX/DEMYX schematic and symbol

 For this schematic we are to include an inverter in our design so the cell only needs one select input which is S and Si is generated by the inverter.

Schematic

Symbol

Simulation Schematic and Result

Part 5: Creating a Full Adder

For this part of the lab, we are to draft the schematic of the full adder that is seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS). Create an adder symbol for the circuit and then use this symbol to draft an 8-bit adder schematic and symbol.

Full Adder Schematic

Full Adder (Top)

Full Adder (Bottom)

Full Adder Symbol

Full Adder Layout (LVS and DRC Included)

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