Project - ECE 421L 

Authored by Jose Cortez,

Email Address: cortej2@unlv.nevada.edu

Lab Date: Nov 13, 2019

Project description (first half)

Design a circuit that takes a 9-11 MHz clock signal and generates a 36-44 MHz clock signal. In other words, design x4 clock multiplier. 

The input clock is multiplied by 4 and output. Assum the input clock signal has a 50% duty cycle.

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the overall idea of the x4 clock multiplier is shown below. The input signal is expected to be a signal between 9-11 MHz and the output 

signal is expected to be 36-44 MHz.

There are two stages because each stage mutliplies the signal frequency by 2. There are buffers applied to the right of each 

XOR for the purpots of outputting sharp square signals, not for adding additional delay to the signal.

Purpose of XOR gates:

The XOR truth table is shown below.

The
XOR gate produces a x2 signal because of the way it is taking in it’s
two signals. Both signals originate from the same source, but one
of them is 

delayed
due to the buffer. This delay allows the input and output to be:
00->0, 10->1, 11->0, 01->1. This pattern is repeated and
appears as the x2 signal. 

The same XOR gate was used for both stages.

Purpose for the buffers after XOR gate:
these
buffers cause the output of the XOR gate to be more square shaped. The
buffers consist of inverters which have a 20/1 ratio as seen below.

The symbol for the clock multiplier is shown below.

Tests: 

change in VDD

Test conditions freq=9.09 MHz, VDD= 4 V
Test conditions freq=9.09 MHz, VDD= 4.5 V
Test conditions freq=9.09 MHz, VDD= 5.5 V
Test conditions freq=9.09 MHz, VDD= 6 V

Tests: 

change in frequency

Test conditions freq=7 MHz, VDD= 5 V Period of voltage source is 140 ns
Test conditions freq=8 MHz, VDD= 5 V Period of voltage source is 125 ns
Test conditions freq=10 MHz, VDD= 5 V Period of voltage source is 100 ns
Test conditions freq=11 MHz, VDD= 5 V Period of voltage source is 90.9 ns
Test conditions freq=12 MHz, VDD= 5 V Period of voltage source is 83.3 ns
Test conditions freq=13 MHz, VDD= 76.9 V Period of voltage source is 140 ns

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 Project Part 2:

Below is the layout for the first stage buffer used in the clock multiplier, as well as other relevant screenshots.

Symbol
Layout
DRC
LVS

Below is the layout for the second stage buffer used in the clock multiplier, as well as other relevant screenshots.

Symbol
Entire layout
Close up of 1st half
Close up of 2nd half
DRC
LVS

Below is the layout for the XOR gate used in the clock multiplier, as well as other relevant screenshots.

Symbol
Layout
DRC
LVS

Below is the layout for the buffers applied at the right side of the XOR gates, as well as other relevant screenshots.

Symbol
Layout
DRC
LVS

below is the clock multiplier layout 

clock mutliplier LVS

clock multiplier DRC

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The link to the files can be found here