Lab 8: EE 421L
Generating a test chip layout for submission to MOSIS for fabrication
Authored by: Kaylee Spencer & Jose Cortez
Email: spenck3@unlv.nevada.edu & cortej2@unlv.nevda.edu
Due: 12/04/2019
Lab Description: Form
into groups of 3 students that will put the test structures on the
chip. Each test circuit should have its own power but ground should be
shared between the circuits. Ground should be pin 20. Power should not
be shared between the circuits so that a vdd!-gnd! short in one circuit
doesn’t make one of the other circuits inoperable.
Prelab
We
first needed to back-up all of our work from the lab and the course.
Next we went through the Cadence Tutorial 6. Some screenshots from the
tutorial are shown below.
Lab
Our chip should include the following test structures:
One, or more if possible, course projects
A 31- stage ring oscillator with a. buffer for driving a 20pF off-chip load
NAND and NOR gates using 6/0/6 NMOSs and PMOSs
An inverter made with a 6/0.6u NMOS and a 12.06 PMOS
Transistors,
both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each
device are connected to bond pads (7 pads + common gnd pad)
Using
the 25k resistor laid out below and a 10k resistor implement a voltage
divider (need only 1 more pad above the ones used for the 25k resistor)
Part 1
Course project:
Schematic:
Symbol:
Layout:
Pin 1: Output – “Out”
Pin 2: Input – “In”
Part 2
31-Stage Ring Oscillator with Buffer:
Inverter:
Schematic:
Symbol:
Layout:
31-Stage Ring Oscillator:
Schematic:
Symbol:
Layout:
Buffer:
Schematic:
Symbol:
Layout:
Pin 3: Output – Out
Pin 4: Input – Vdd_ring_osc
Part 3
NAND Gate:
Schematic:
Symbol:
Layout:
Pin 5: Output – AnandB
Pin 6: Input 1 – A
Pin 7: VDD – Vdd_nand
Pin 8: Input 2 – B
Part 4
NOR Gate:
Schematic:
Symbol:
Layout:
Pin 9: Output – AnorB
Pin 10: VDD – Vdd_nor
Pin 11: Input 1 – A
Pin 12: Input 2 – B
Part 5
Inverter:
Schematic:
Symbol:
Layout:
Pin 13: Output – Ai
Pin 14: VDD – vdd
Pin 15: Input – A
Part 6
Transistor:
NMOS:
Schematic:
Symbol:
Layout:
Pin 16: Drain – D
Pin 17: Gate – G
Pin 18: Source – S
PMOS:
Schematic:
Symbol:
Layout:
Pin 21: Bulk – B
Pin 22: Source – S
Pin 23: Gate – G
Pin 24: Drain – D
Part 7
Voltage Divider:
Schematic:
Symbol:
Layout:
Pin 25: Input – in
Pin 26: Output – out
Part 8
Overview:
Below
is an image of how the chip’s pads corresponds to the pins of the 40
pin DIP package from MOSIS as well as a table of our pin assignments.
We also added proof of our schematic properly preforming DRC and our
extracted layout preforming LVS.
