Lab 5 - ECE 421L 

Authored by Jose Cortez,

Email Address: cortej2@unlv.nevada.edu

Lab Date: Sep 25, 2019-Oct 2,2019

Lab description:

In this lab we created schematics, layouts, extracts and simulations of CMOS inverters. The simulations took place

in cases where there were 1 and 4 inverters using both spectre and Ultrasim simulators.

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Prelab:

I was able to create the schematic, symbol, and layout of the CMOS inverter using a PMOS and NMOS. After which I LVS to make sure the netlist 

between the schematic and extracted matched.

I then simulated the voltage transfer curves from the schematic seen below.

I then created a symbol for that schematic.

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Lab:

• Draft schematics, layouts, and symbols for two inverters having sizes of: 

• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)

• 48u/24u where the devices use a multiplier, M = 4

I began by creating a new folder (copied from the prelab tutorial 3) titled lab5 and opened a schematic cellview.

I then created a symbol for that schematic.

The layout for the inverter with multiplier 1 was created and is shown below.

The layout for the inverter with multiplier 4 was created and is shown below.

The successful LVS results for both inverters can be seen below.

In order to simulate the newly created inverters, I created a new cell library titled sim_inv_mult_1 for the first inverter results.

Below are the schematics and simulation results for the inverter with multiplier 1 using both spectre and Ultrasim

(spectre uses red graphs and Ultrasim uses blue graphs)

(spectre uses red graphs and Ultrasim uses blue graphs)

The Inverters used can be found through this link

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