Lab 3 - ECE 421L 

Authored by Jose Cortez,

Email Address: cortej2@unlv.nevada.edu

Lab date: Sep 11, 2019

  

Lab description: 

In this lab, I applied the resistors I made in tutorial 1 to recreate the the DAC I created in lab 2. 

I also discuss how to determine the width and length from MOSIS using the SCMOS_SUBM 

compatible mappings.

 

Prelab 3:

I have gone through the steps of tutorial 1, below is the layout of the resistor voltage divider.

prelab_layout

   
   

Lab 3:

how to select the width and length of the resistor?

start
by referencing the process information from MOSIS. The references for
the process information from mosis are shown below. 

They
outline they outline the scale of design, which is relative to the
process. In class we use the C5 process with a lambda of 0.30
microns. 

Well width is also defined in the mosis page

SCMOS_SCMOS_submicron
compatible_mappings_for_MOSIS_CMOS
   
   
   

The calculations for width and length are shown below. They outline how to solve for the length of the n-well given the square resistance, width, and total resistance desired.

hand_calcs

  

   

   

I then opened the schematic of the DAC I created in lab #2 as shown below.

I am using the lab2 folder since I will be using the schematic I made for lab#2 for this lab.

folder_path_to_DAC_schematic

schematic

   

   

   

I then replaced resistors with the layout of voltage dividers I created in tutorial 1.

Layout of one resistor and the entire DAC are shown below

layout_of)single)resistor

   

   

entire_DAC_layout

   

   

B9

B8

B7

B6

B5

B4

B3

B2

B1
B0
   
   
   
I then went through verify-->DRC with no errors and ran verify-->LVS as shown below
DRC
LVS

The link to the folder with the designs used in my lab 3 are here.

   

   

   

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