Lab 2 - ECE 421L 

Authored by Jose Cortez,

Email Address: cortej2@unlv.nevada.edu

Lab date: Sep 4, 2019

  

Lab description:

In this lab we used n-well resistors to implement a 10-bit DAC.

 

Prelab (parts 1-3)

   

Part 1)

locate and simulate the ideal ADC to DAC schematic given to us on the lab 2 webpage. 

The file should be located in the lab 2 file as shown below.

location_of_ideal_schematic_for_prelab

Below is how the schematic should look like.

schematic_for_ADC_DAC

Below is what the simulation should look like.
sim_results_for_prelab

   

   

Part 2)

I removed the lower wires (less significant bits) connected to the 10_bit_ideal_DAC, this will cause the lesser significant bits to not be received by the DAC. The ADC will only be able to deliver the higher bits (the three most significant bits) to the DAC, the rest of the bits will still be viewable in the simulation to observe their behavior..


The DAC will still output a signal similar to the input signal, but since it is missing the lesser significant bits, it will appear less accurate. 


The more significant bits represent the most amount of voltage in the signal. The most significant bit representing the highest amount of voltage among the other bits.


The lesser significant bits represents the smaller changes in the input signal,they represent smaller amounts of voltage, since they are removed, the output signal will be missing the smaller changes and appear less accurate when compared to the input voltage(less smooth).


The simulation results include Vin,Vout and the lesser bits not received by the DAC. Everytime one of the lesser bits is on, there would be a small amount of voltage applied to vout to make it more similar to vin.

Below is the altered schematic and simulation results.


   

altered_prelab_schematic
   
altered_schematic_sim

   

   
Part 3)

How to determine least significant bit from the converter:

The least significant bit is the one that contributes to the smallest amount of voltage change.

This can be identified by looking at when it should be on, such as simulation results like the one

shown above. It should be ON (a value of 5V) when there are small changes to the input.

 

 

Lab 2

 

-Design of a 10-bit DAC using an n-well R of 10k

 To start the lab, I made a copy of the folder for the ideal_10_bit_DAC and renamed it Mydesign_10_bit_DAC.

I reconfigured the ideal DAC so that it may consist of resistors (as shown below)

Mydesign_full_image
Mydesign_top
Mydesign_bottom
   
   
The edited symbol view is shown below, only the name is changed.
Mydesign_symbol
   
   
   
 I then created a copied folder of the last sim (which was the prelab) to make a
new simulation, but this time it would include the DAC I created (Mydesign_10_bit_DAC)
sim_setup_folder

   

   
I then simulated the circuit using the DAC I created in that folder, the schematic and results are shown below.
sim_Mydesign_schematic

sim_Mydesign_results

   
   
   
Below are the hand calculations for calculating the least significant bit (LSB) voltage, estimating time delay for a
capacitive load and method for simplyfying the circuit by creating R equivalent resistors
hand_calcs
   
   
   
Below is the schematic and results of the DAC when all the inputs (except B9) are grounded. B9 is connected
to a pulse source and there is a 10 pF capacitor load. 
Mydesign_inputs_grounded_schematic

Mydesign_inputs_grounded_results

   
   
   
I then set inputs of the DAC back to the outputs of the CAD and ran a simulation with a resistive load.
Mydesign_resistive_load_schematic

Mydesign_resistive_load_results

   
   
   
I then ran a simulation with a capacitive load (schematic and results shown below)

Mydesign_cap_schematic

Mydesign_cap_results

   

   

   

Finally, I ran a simulation with a resistive and capacitive load
Mydesign_res_cap_schematic

Mydesign_res_cap_results

   

-What if the resistance of the switches of the DAC (shown below) aren't small? 

   

DAC_visual_representation

If the resistance of the switches were not small compared to R, then it would decrease 

Vout. In every subsection of the DAC (in between nodes) there is a smaller output 

proportional to Vout. The smaller outputs are Vout*1/2,Vout*1/4,Vout*1/16 and

so forth. increasing the resistance of the switches changes these propotional smaller

outputs and would thus reduce Vout. Having more voltage drops would mean the output

voltage gets reduced.

   

      

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