Lab 2 - EE 421L - FALL 2019
Design of a 10-bit digital-to-analog converter (DAC)
Relationship between Vin, B[9:0], and Vout:
The B[9:0] is a 10-bit binary value that is converted from the input voltage (Vin) due to the ADC. The ADC takes in an analog signal (Vin) and converts it into a digital signal (0V->5V or logic 0 or 1), which
produces the 10-bit binary value. The 10-bit value is then used as an input into the DAC and outputs an analog signal (Vout). The DAC converts a digital signal into an analog signal.
LAB
To get started with lab 2, it is important to sign into MobaXterm, cd into the CMOSedu directory, and run Cadence. From the prelab, I have already uploaded/unzipped the given lab 2 files that
contains the ADC and DAC schematics.
The goal of this lab is to copy an equivalent DAC (Figure 30.14) from the book and replace it with the ideal DAC on the top-layer schematic (sim_ and perform several edits and various simulations with the new schematic.
Image shown below is the new DAC schematic that will be used to replace the old DAC schematic.
First task I did was to copy the ideal DAC schematic and rename it into "My_10bit_DAC." I also made a new top-layer schematic which is "sim2_Ideal_ADC_DAC" which
includes the new DAC schematic.
Here is the ideal DAC schematic transformed into the new DAC schematic (zoomed in) and with the new DAC schematic replacing the old DAC schematic on the layout view.
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Symbol Creation:
The following image below is the symbol created from the 2nd image shown above (DAC).
How the symbol is created: (From the resistor schematic) Create->Cellview->From Cellview. Following window will pop up. Make sure to select "symbol."
Notice that because the vrefp, vrefm, and vdd pins are already plotted on the layout view, there is no need to connect those pins within the DAC module. However, it is still necessary for
those pins to be included within the schematic. They still exist but are connected with "noConn's."
Prior to simulating, it is helpful in this lab to force the simulation to converge to prevent any convergence issues when simulating. To do this, I have to open the ADE L window and go to
Simulation->Option->Analog and type in the following settings:
The following was my simulation for "sim2_Ideal_ADC_DAC" with the new DAC schematic in comparison with the old schematic from the prelab.
before: after:
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Notice that they are about the same graph.
Different Simulations to Illustrate Understanding of ADC and DAC
The two images shown below illustrate the functionalities of the ADC and DAC.
Vin amplitude @ 5mV, Offset @ 5mV Vin amplitude @ 10mV, Offset @ 10mV
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The two images above are far different compared to the images shown previously with the simulation of the ideal or the new DAC with a greater input pulse.
It is obvious that the two graphs have a Vout signal that have a more visible/larger 'staircase' graph and perhaps have a lower resolution as the graphs seem to be leaning towards
the look-alike of a square waveform rather than a nice, solid, sinusoidal curve. According to the left image, the minimum change in Vout is around 4.88mV. This value is the same
as the value calculated for when ONLY the LSB (or least significant bit) of the 10-bit value influences Vout (when only the LSB is at 5V or is a logic 1). The trend in the graphs is dependent
on the change of the input pulse (Vin): the higher the pulse (Vpp), the more 'staircases' seen on the graph making it look a lot more identical to a sinusoidal curve.
Calculating the LSB
The LSB is calculated as follows:
If we plug in our values for VDD and N:
1 LSB = 5V / 2^10 ~ 4.88mV
The value of Vout will be 4.88mV only when the 10-bit value represents 0000000001 (only LSB is high).
The graph below shows Vout when the input Vpp and offset is at exactly 4.88mV (Vout is a square waveform).
How to Calculate Output Resistance of the DAC
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To get the output resistance of the DAC, you must start at the bottom of the schematic and work your way towards the top. At the bottom, there are two 10k resistors that represent the 2R
and you have to calculate the parallel equivalent resistance of the two (ans = 10k). Once the equivalent resistance is obtained, you can then combine it in-series with the 10k resistor just right
above it to form another 2R. This process will then repeat, until the top of the schematic is reached.
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R, C, and R/C Loads
1. Resistor (10K) load:
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When a resistor load is added onto the DAC, Vout can be obtained using a voltage divider. As shown above, loading a 10k resistor will result in an output voltage that is half the
magnitude of the input voltage.
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In a real circuit, the switches seen above (outputs of ADC) are implemented with transistors (MOSFETs)
Backing up my files:
- Compress the file
- Upload the file onto my Google Drive
