Lab 6 - ECE 421L
Authored
by Yared Abraha,
abrahy2@unlv.nevada.edu
10/23/19
Lab
description
Desingn layout and simulation of a cmos NAND gage, XOR gate and FULL ADDER
pre lab
Completing tutorial 4 wich was completed as seen below
The
basic thing in tutorial 4 is to desing, layout, and simulate a NAND
gate, including every steps the tutorial is completed as seen below.
The schematic of the nand gate
symbol of the nand gate with my initials on it.
simulation of the single input nand gate is seen below
the lay out of the NAND gate and it shows that it is DRC clear.
LVS of the NAND gate is shows that it matches.
Lab:
step 1 draft the schematic of two input NAND gate and 2 input XOR gate using 6u/0.6u MOSFETS NMOS and PMOS
the NAND gate schematic has been desinged in the tutorial as seen above so we don't need to redo the nand gate.
XOR gate shcmematic is seen below .
This is the symbol of the XOR gate with my initals on it
The layout of the XOR gate and it shows that it is DRC clear.
the extracted view of the XOR gate
the result wich shows that our XOR maches with schematic or it is LVS clear
STEP 2
using
specture simulation the logical operation of the gates for all 4
possible inputs (00, 01, 10, 11), Thsi simulation is for all the
NAND, XOR and INVERTER simulation both the NAND and XOR has two inputs.
we
can see on the figure above that they all work correctly. Also the
changes in the logical output are not as perfect as the theortical
assumption, we can see as an example that when the input pulse change
from low to high of high to low, there is a rise time and fall time
that prevents the change in output to change perfectly.
This may cause glich in devices specialy those devices with memory since the value is not perfectly consistent.
| A | B | Ai | NAND | XOR |
| 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 |
STEP 3: Using these gates draft the schematic of the full adder. create a symbol for the full adder.
Simulate, using spectrure, the operation of the full adder using this symbol.DRC and LVS your full adder.
full adder schematic
full adder layout
DRC result of the full adder
full adder extracted.
LVS results of the full adder
full adder symbol together with the connections to simulate it.
simulation results of the full adder
Truth table of the full adder
| A | B | Cin | SUM | CARRY out |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
A bakc up file is created.
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