Lab 5 - ECE 421L
Authored
by Yared Abraha,
abrahy2@unlv.nevada.edu
10/8/19
Lab
description
Desing, layout, and simulation of a CMOS inverter
pre lab
completing tutorial three wich was completed as seen below
A
schematic cell view of an inverter was created using 4 terminal nmos
and pmos. the length and width of the pmos and nmos in the inverter are
12u/6u and 48u/24u with a minimum lenth of 0.6u as seen below.
first this inveter is the 12u/6u
. 
using cell view from cell view a symbol is created as follows.
A layout view is created for the inverter.
using the design check rule the layout was checked and it passed the test( DRC).
pins vdd, gnd, A, Ai were created for the symbol, and again passed the DRC test.
The layout is extracted as follows.
An aditional check was made, on this time the check rule was between the schematic and the layout (LVS) and it passed.
simulating the operation of the inveter with out specifying Vdd!
After
Vdd! is specifyed as following in the simulation schematic that we
created for simulating the inverter, the simulation result of the
inverter changed to this form.
Second, following every procedure like the previous 12u/6u inverter 48u/24u inverter was created as shown below.
since
desing this inverter is essential for doing simmulation at the end by
attaching different laod capacitancess a DRC and LVS check are done
care fully as shown below.
this the symblol, no new method or procedure is used it is just the previous method it self.
chreting the lay out, assigning pins and DRC cheks
extracted view of the layout.
LVS of the schematic and the layout .
Simulating
12u/6u inverter using different value of capacitacne attached to
it. The capacitances used here are 100f F, 1p F, 10p F, 100p F and the
rulsut is going to be observed as the capacitance value changes
from 100f F up to 100p F.
In the following simulation schematic
a capacitance value of 100f F is asuumed, the inverter is instantiated
form the symbol of 12u/6u and all essentioal elements are
insantiated using the same method like the previous lab reportes.
The
simulation is also done using two methods the SPICE and Ultrasim. the
folloing simulation is done using SPICE and we will see simulation
using Ultrasim.
using
transint reponse and using A and Ai we also added the model library for
the pmos and nmos following the path provided in the lab instruction we
simulated the inverted connected with capacitance and it gave us the
folloing results seen below.
As commented below the following reuslt is for 100f F capacitance.
1pf capacitance
10pf capacitance
100pf capacitacne
As
seen from the graphs we can conlude that when the input rises the out
put falls and when the input falls the out put rise, we can also see
that the input has a sharper slope than the out put this means the out
put takes a littel while to change in comparison with the input.
Inaddition to this when the capacitace value increase the out put takes
longer time to change from the low to hing valule or from high to low.
This
is also the simulation of the 48u/24u which follows the same
procedure as the 12u/6u but it gives as slightly different result for
different capacitance value than the previous inverter.
100ff capacitance
1pf capacitance
10pf capacitance
100pf capacitacne
In
comparison with previous one, this one has high gain this means our out
put changes value faster from high to low, but they both does the
inversion proccess. If we concider the highst capacitance in this
specific inverters which is 100pf, the 48u/24u has faster fall time
than the 12u/6u.
simulation using Ultrasim was made and it has
no difference with simulation using SPICE so instead of wasting space i
chose to change the simulation of the first inverter of the 12u/6u
using Ultrasim and simulation of the lower inverter using SPICE, so if
you wish to see simulation using Ultrasim go to the first inverter and
simulation using SPICE go to the secon inverter.
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