Lab 2 - ECE 421L 

Authored by Yared Abraha,

abrahy2@unlv.nevada.edu

9/11/19

Lab description

Design of a 10-bit DAC

pre lab

According to the steps described in the lab instruction, the following fill uploaded to the CMOSedu directory.

it gave the following results after simulated.

Lab procedures:

The schematic of 10 bit DAC, using R=10k value

I created a symbol from the schematic

the symbol is instantiated to the given schematic.

the simulation result

A 10k ohm load resistance is added

simulation result after the 10k ohm load is added

we then replace the 10ohm load by 1pf capacitance

then after we add to the load both the capacitor and the resistor

the simulation result optained by additing the resistor and the capacitor to the load

Then we remove the voltage sourse and we replace it with pulse voltage sourse from 1 to 5, and the 10k resistance in the load is removed. The pulse voltage sourse is applied to b9, the rest of them are grounded.

The simulation result is below. The total resistance is is R=10, which is calculated by tuning off all the sourse voltages and the capacitance is 1pf:

td=0.7RC=7ns

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