Lab Project - ECE 421L
Project design a
circuit that takes a 9-11 MHz clock signal and generates a 36-44 MHz clock
signal. In other words, design x4 clock multiplier. The input clock is
multiplied by 4 and output. Assume the input clock signal has a 50% duty cycle
A logic gate that can perform this operation is an XOR gate
because the output of the XOR gate is high only when both inputs have different
value, otherwise the output is low. Using this method the same frequency input
can be given to the XOR gate in which one of the inputs is delayed so that the output
of the XOR gate is 2x of the input frequency. After that feeding the output of
the XOR to a second XOR which performs the same function gives as the desired
frequency.
XOR gate was made
using a PMOS and NMOS in which both of the MOSFETS used have the same size 6u/6u
and length of 0.6u
The delaying elements of one of the inputs of the XOR are
made using an inverter.
Different inverters with different size are used(td=0.7RC) and resistance depends on length of the MOSFET
This is one example of the inverters used in which all inverters are similar, their difference is the size of the MOSFET
The first delay of the first XOR was made from sequence of inverters in which, the first inverter was there inverters represented precisely using bus which has the size of 6u/6u, 6u and the second one also has two inverters in it which are 6u/6u, 12u increasing the length of the MOSFET increases the delay. At the end there inverters are used in a row with a minimum length which has less delay but important for squaring (12u/6u, 0.6u) the wave, in addition to this the capacitance of the MOSFET is C=Cox’LW in which reducing the length reduces capacitance in which it results a sharp edge wave.
Symbol of first delay element, two inverters (12u/6u, 0.6u) added at the end even to make the output signal more square locking wave.
The simulation of the first XOR is seen below, which multiplies
the input frequency by 2.
In the simulation the frequency used is 10 MHz this means the period is 1/f=100ns and the input frequency has 50% duty cycle. As seed the delayed signal is delayed 25ns and my result is approximate 25.8ns.
The second delay of the second XOR was made from sequence of inverters in which, the first inverter was two inverters represented precisely using bus which has the size of 6u/6u, 6u and the second inverter also has a dimention 6u/6u, 12u increasing the length of the MOSFET increases the delay. At the end there inverters are used in a row with a minimum length which has less delay but important for squaring (12u/6u, 0.6u) the wave, in addition to this the capacitance of the MOSFET is C=Cox’LW in which reducing the length reduces capacitance in which it results a sharp edge wave.
Symbol of second delay element, two inverters (12u/6u, 0.6u) added at the end even to make the output signal more square locking wave.
The simulation of the second XOR is seen below, which multiplies
the input frequency by 2.
In the simulation the input frequency used is 2x10 MHz this
means the period is 1/f=50ns and the input frequency has 50% duty cycle. As seed
the delayed signal is delayed half of 25ns which is supposed to be 12.5ns and
my result is approximate 11.5ns.
At the end to form 2X frequncy multiplier the Two XOR gates
are combined to form a complete symol of the 4X frequency multiplier.
In this simulation we have used a VDD 5V and f of 10MHz
The next simulation have used a VDD 8V and f of 10MHz
The next simulation have used a VDD 4V and f of 10MHz
PART II-LAYOUT
One of the main building blocks for
the frequency multiplier is inverter, because it is the inverter that gives us
the required delay for the second input of the XOR gates. A string of inverters
with different sizes of PMOS and NMOS are connected to gather to form the
required delay, which are delay 1 and delay 2 in my circuit. The second part of
my frequency multiplier is the XOR gate, in which it takes the two inputs (the
delayed one and the direct input) and outputs the required multiplied frequency
output.
Instead of creating all my layout
of the frequency multiplier in one cell, I created an individual layout of each
parts which are used in the frequency multiplier and instantiated those parts
in to the layout of the frequency multiplier.
Schematic
The schematic of my frequency multiplier with individual
parts.
1. Delay 1- which is the first delay in the circuit
which has 8 inverters of different size connected in series
2.
XOR 1- the first XOR gate that doubles the input
frequency.
3.
Squares the wave- inverters that squares out output
frequency from XOR 1.
4. Delay 2 - this delays the output of the first
XOR gate.
5. XOR 2 – the second frequency multiplier of the
doubled frequency.
The layout of a single inverter is
seen below
Layout
DRC
Extracted view
This
inverter has a PMOS size of
12u/0.6u and an NMOS size of 6u/0.6u which is directly used in the
inverters
which are used to square the output of the multiplied frequencies. and
the three inverters which are foun at the end of both delay elements.
Below is also the layout of an
inverter which has a length of 6u for both PMOS and NMOS and the length of
both is 6u
The next picture shown below is
delay1 (25ns delay time) in which it has 8 inverters on it. The inverters on
this delay have different length in order to get the desired delay. The first
three inverters has length of 6u and width of 6u for both PMOS and NMOS, while
the second two inverters has a length of 12u and a width of 6u for both PMOS
and NMOS, and the last three inverters has a PMOS with length of 0.6u and width
of 12u and NMOS length of 0.6u and width of 6u.
Layout
The first XOR gate is also shown below, the XOR gate
has also 6 PMOS and 6 NMOS both the PMOS and the NMOS have the same size which
is 6u/6u with minimum length. The XOR is used to double the frequency of the
given input, in which one input of the XOR gate is connected with the direct
input and the other terminal is connected with the delayed input
Layout
After the XOR gate what we have is
the two inverters that are used to square the wave these two inverters have
minimum length which is 0.6n and a width of the MOSFETS is 12u/6u. Even number
of inverters are used because the output is not needed to be inverted.
The next element in the frequency
multiplier is delay2 (12.5ns delay time) which has 6 inverters, these inverters
are connected in way that output of one is connected to the input of the other.
The first two inverters have size of 6u/6u with a length of 6u, the second
inverter has width of 6u/6u and length of 12u, and the last 3 inverters have
the same size which is 12u/6u and a minimum length.
Layout
LVS
After the second delay their will be an XOR gate which has the same dimensions as the first XOR gate we have seen previously. The input of this XOR gate are the output of delay2 and the out of the first XOR gate which passed through two inverters to be squared.
The last two parts are the inverters this two invert this two inverters are used to square the wave output of the XOR gate and make it to have a square shape. Since we have seen those two inverters layout above after the output of the XOR 1 we are not going to repeat them in here.
The final 4x frequency multiplier is
seen below. it is the combinaition of all those parts liseted above so
to make the layour of the frequency multiplier the layout of each part
was instantiated and combined using metal 1 and metal 2.
Layout
LVS
All the layouts seen above are made
based on the sizes used in the schematic of the 4x frequency multiplier. As
explained in the schematic change the size of the MOSFETS was essential to find
the desired delay in our inputs to the XOR gates and over all to find a
reasonable delay from the 4x frequency multiplier.
Td=0.7RC
According
to this formula increasing the length or decreasing the width of the MSOFET
increases the delay time because it increases resistance, but playing with the
length of the MOSFET was a preferable one since it is hard to layout a MOSFET
with really small width.
As
seen above all my layouts satisfy Design Rule Check (DRC) clear which shows that the layout satisfies the given rules.
In addition to that all my layout matches with schematic as seen from the
Layout Versus schematic (LVS)