Lab 7 - ECE 421L 

Authored by Esteban Tuquero

email:tuqueroe@unlv.nevada.edu

November 11, 2018

Lab Description

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

Pre-lab

Go through Cadence Tutorial 5

All files have been backed up on Google Drive

4-bit Word Inverter

Schematic	Symbol

Schematic	Simulation

8-bit input/output of NAND, AND, NOR, OR, and inverter

Schematic of  8-bit AND gate	Symbol of  8-bit AND gate
Schematic of  8-bit NAND gate	Symbol of  8-bit NAND gate
Schematic of  8-bit OR gate	Symbol of  8-bit OR gate
Schematic of  8-bit NOR gate	Symbol of  8-bit NOR gate
Schematic of  8-bit inverter	Symbol of  8-bit inverter

Simulation of Gates

For simulating the gates, I decided to do them all in one schematic and simulation. I separated the simulations so that the results would not look so clustered. I also added capacitors on the outputs to further show the effects of the capacitors as the capacitor increases. Again, it is shown that the greater the capacitor is the slower it takes for the output to reach the correct values.

Schematic of simulating all the 8-bit gates

Simulation of 8-bit AND gate

Simulation of 8-bit NAND gate

Simulation of 8-bit inverter

Simulation of 8-bit OR gate

Simulation of 8-bit NOR gate

2-to-1 DEMUX/MUX

Schematic of a 2-to-1 DEMUX/MUX	Symbol of a 2-to-1 DEMUX/MUX

For the 2-to-1 DEMUX/MUX, I made A, B and Z input/output nodes so that when we simulate the DEMUX and the MUX we just need to reverse the inputs and outputs of A,B, and Z.

Simulation of 2-to-1 DEMUX/MUX

Schematic for simulating DEMUX	Simulation of Demux
Schematic for simulating MUX	Simulation of Mux

 8-bit DEMUX/MUX

Schematic of 8-bit DEMUX/MUX	Symbol of 8-bit DEMUX/MUX

Simulation of 8-bit DEMUX/MUX

Schematic for simulating 8-bit DEMUX	Simulation of 8-bit DEMUX
Schematic for simulating 8-bit MUX	Simulation of 8-bit MUX

Full Adder

Schematic of Full Adder	Symbol of Full Adder
Layout and DRC of Full Adder	Extracted view and LVS of Full Adder

8-bit Full Adder

Schematic of 8-bit Full Adder	Symbol of 8-bit Full Adder

Layout and DRC of 8-bit Full Adder

Extracted view and LVS of 8-bit Full Adder

Simulation of 8-bit Full Adder

Schematic for Simulating 8-bit Full Adder	Simulation of 8-bit Full Adder

All the files for this lab can be found here.