Lab

Lab 6 - ECE 421L

Authored by Esteban Tuquero

email: tuqueroe@unlv.nevada.edu

October 24, 2018

Lab description

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Prelab
Go through Cadence tutorial 4
All files have been backed up on google drive
file:///C:/Users/Patron/Desktop/lab6/backup.JPG

file:///C:/Users/Patron/Desktop/lab6/backup.JPG

NAND Gate
Draft the schematics of a 2-input NAND gate using 6u/0.6u MOSFETs (both NMOS and PMOS)


Schematic	Symbol


Layout	DRC	Extracted View	LVS

XOR Gate
Draft the schematics of a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)


Schematic	Symbol


Layout	DRC


Extracted View	LVS

Gate Simulation
Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)


Gate Simulation Schematic	Simulation Results

Truth Table
A	B	AnandB	AxorB	Ai
0	0	1	0	1
0	1	1	1	1
1	0	1	1	0
1	1	0	0	0

From the above simulation, one can see that the XOR, NAND, and NOR gates are working properly. When looking at the simulation results, one can see that in the transition from 01 to 10 (A="0", B="1" -> A="1", B="0") the XOR output drops down to 0 for a fraction of a nanosecond. This is a result of the rise time and fall time of the two inputs. Since they are not perfectly in sync, this will cause a glitch in the transition as A rises to "1" and B falls to "0".

Full Adder
Using these gates, draft the schematic of the full adder


Schematic	Symbol

file:///C:/Users/Patron/Desktop/lab6/ADDER_lay.JPG

Layout

file:///C:/Users/Patron/Desktop/lab6/ADDER_drc.JPG

DRC

file:///C:/Users/Patron/Desktop/lab6/ADDER_ext.JPG

Extracted View

file:///C:/Users/Patron/Desktop/lab6/ADDER_lvs.JPG

LVS

Full Adder Simulation
Simulate, using Spectre, the operation of the full-adder using this symbol


Full Adder Simulation Schematic	Full Adder Simulation Results

Full Adder Truth Table
A	B	Cin	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

By comparing the truth table and the simulation results, one can see that the designed full adder is working as it should be. However, there are still see glitches at 200, 400, and 600ns for S and at 600ns for Cout. Again this is due to the rise and fall time of the edges on the inputs.

All files from this lab can be found here.

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