Lab 5 - ECE 421L 

Authored by Esteban Tuquero

Email: tuqueroe@unlv.nevada.edu

October 9, 2018

 

Pre-lab work

 http://cmosedu.com/jbaker/courses/ee421L/f18/students/tuqueroe/lab5/back1.JPG

http://cmosedu.com/jbaker/courses/ee421L/f18/students/tuqueroe/lab5/back2.JPG

All files have been backed up on google drive.

Lab

Design, layout, and simulation of a CMOS inverter

 

Schematics of both 12u/6u inverter and 48u/24u inverter with 4 fingers on the PMOS and the NMOS. 

file:///C:/Users/Student/Desktop/lab5/not_schematic.JPGfile:///C:/Users/Student/Desktop/lab5/not4_schematic.JPG
12u/6u Inverter48u/24u Inverter
 
Layout, extraction, DRC, and LVS of 12u/6u inverter.
file:///C:/Users/Student/Desktop/lab5/not_layout.JPGfile:///C:/Users/Student/Desktop/lab5/not_DRC.JPG
LayoutDRC
file:///C:/Users/Student/Desktop/lab5/not_extracted.JPGfile:///C:/Users/Student/Desktop/lab5/not_lvs.JPG
Extracted ModelLVS with Net-list Match
 
Layout, extraction, DRC, and LVS of 48u/24u inverter.
file:///C:/Users/Student/Desktop/lab5/not4_layout.JPGfile:///C:/Users/Student/Desktop/lab5/not4_drc.JPG
LayoutDRC
file:///C:/Users/Student/Desktop/lab5/not4_extracted.JPGfile:///C:/Users/Student/Desktop/lab5/not4_lvs.JPG
Extracted ModelLVS with Net-list match
 
Simulation of Inverters
For the simulations of the intverters I used the same set up to test both inverters. The parameters for the voltage pulse are as follows: Voltage 1 = 0V, Voltage 2 = 5V, Delay time = 5ns, Rise time = 1ns, Fall time = 1ns, and Pulse width = 10ns. For vdd I set it up as a global variable by opening the ADE L -> Setup -> Stimuli, and setting vdd = 5V. It was also necessary to show the simulations from both the Spectre and UltraSim simulators. The following pictures show the schematics for both simulations. Note that c = Ci so that I can use parametric analyse to show the curves for the different capacitor values.
file:///C:/Users/Student/Desktop/lab5/not_simulation_schematic.JPG
12u/6u Inverter Simulation Schematic
file:///C:/Users/Student/Desktop/lab5/not4_simulation_schematic.JPG
48u/24u Inverter Simulation Schematic
 
Spectre simulation with parameters for both inverters.
file:///C:/Users/Student/Desktop/lab5/not_spectre_params.JPGfile:///C:/Users/Student/Desktop/lab5/not_spectre_graph.JPG
12u/6u Inverter Spectre Simulation Parameters12u/6u Inverter Spectre Simulation
file:///C:/Users/Student/Desktop/lab5/not4_spectre_params.JPGfile:///C:/Users/Student/Desktop/lab5/not4_spectre_graph.JPG
48u/24u Inverter Spectre Simulation Parameters48u/24u Inverter Spectre Simulation
 
UltraSim simulation with parameters for both inverters.
file:///C:/Users/Student/Desktop/lab5/not_ultra_sims_params.JPGfile:///C:/Users/Student/Desktop/lab5/not_ultra_sims_graph.JPG
12u/6u Inverter UltraSim Simulation Parameters12u/6u Inverter UltraSim Simulation
file:///C:/Users/Student/Desktop/lab5/not4_ultra_sim_params.JPGfile:///C:/Users/Student/Desktop/lab5/not4_ultra_sim_graph.JPG
48u/24u Inverter UltraSim Simulation Parameters48u/24u Inverter UltraSim Simulation
 
Conclusion
When comparing the two inverters it is seen that the larger inverter can handle higher capacitive load. This means that there is a less drastic change in the output of the inverters. Also when comparing Spectre with UltraSim there is not that much of a change in the graphs, but UltraSim did run faster than Spectre.

The cells used to generate the images are in lab5_eat.zip

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