Project - EE 421L
Author: David Silic
Email: silic@unlv.nevada.edu
EE421L
Project description:
Our project is an 8-bit serial to parallel converter. The system will take a serial input and a clock signal and output the serial input to 8 parallel bits and an output clock which has a period 8 times that of the input clock.
The fundamental building block of our circuit is the D flip flop. Each D ff is connected to clock, as the first clock goes high D passes the first ff and goes to D0. At the next edge that same D value passes to the second ff and outputs to D1. As this process continues we get an output where D is shifted all by a clock cycle delay for each output.
In order to get a true parallel output we must also have a method of storing the bits as they are shifted through. In order to do this we design anther set of ff with a clock cycle which is exactly 1/8 of the input clock. This is achieved by simply sending the clock through three D flip-flops. The delay of each flip-flop halves the clock cycle. Now we add a second set of 8 D ff controlled by our new slower clock cycle. Our shifted bits are entered into the new FF which only inputs the data every 8 clock cycles. This gives us those 8 serial bits in parall
Schematics and simulations:
Many parts of our project use inverters, below we show the schematic and symbol used in all the schematics.
The fundamental building bock of our serial to parallel converter. We use a Parallel NMOS-PMOS combination to make logic through gate. The circuit takes an input D and a clock signal. The Inverters on the left invert to clock signal to give us a clk_not signal. The clock and clock_not are connected to one of the PMOS or NMOS of the gate, thus D passes through only On clock high. Note the last inverter allows us to get Q and Qnot out.
Now
we simulate the above schematic:
As we can see the output Q(top)
follows the input(bottom) depending where each clock edge
lands.
Using this D flip flop we now build an 8 bit shift
register seen below.
Each D ff is connected to clock, as the first clock goes high D passes the first ff and goes to D0. At the next edge that same D value passes to the second ff and outputs to D1. As this process continues we get an output where D is shifted all by a clock cycle delay for each output. This behavior is shown by the simulation below:
Sim Clock period is 4n.
Din for 8n, or 2 clock period
As
we expect the D input high for to clock input can be seen shifted by
4 ns every output.
Now we design our 1/8th clock converter as we described above.
Here
clock_in has a period of 2u and Clock_out has a period of 16u.
Note we tried to use the same range but in nanoseconds and had some delay from input to output clock. This shows that we should use longer time simulations because low nanosecond sims will likely result in some timing related errors.
The
final serial to Parallel schematic is as follows:
The only thing that remains is to simulate using the following schematic:
For
our simplest sim we simply set D to be One:
Here Clock has a period of 500n, note Clock_out, after clock goes through our ⅛ converter, is 8 times as long, with a period of 4u.
As we can
observe all the bits go to one, and are outputted after the second
clock_out cycle.
D in is twice Clock_out with a period of 8u. Below we use the same Clocks, but we set D to have a smaller period, just 2u.
Layout
We layout, DRC every cell used in the Project
below:
Fist we have the Inverter layout used:
LVS
and DRC check out as we note above!
Now we proceed
to layout the D Flip-Flop, this will be a fundamental building
block
for our circuit:
DRC and LVS for the D FF check out. We now show the layout for our 1/8th clock which is composed of 3 D flip-flops:
DRC and LVS check out. Now we combine 8 of the D Flip-flops together in order to form our shift register.
DRC and LVS check out.
Finally we put each part together to form our final serial to parallel converter layout. The bottom level is made up of the shift register, while the top level is the 1/8th clock and the final 8 D flip-flops which store the parallel bits.
Below we show the different moduals more clearly:
In
addition we provide a more zoomed up view to showcase some of the
wiring:
The
layout DRC's and LVS's!
As we have done with our labs we make sure to save our files on a Google drive account.
File Download HERE
