Lab 8 - EE 421L
EE 421L
David
Silic, silic@unlv.nevada.edu
Marco Muniz, munizm1@unlv.nevada.edu
Nicholas Mingura, mingura@unlv.nevada.edu
Lab Overview:
This lab contains the schematic and layout of Our test chip layout to for submission to MOSIS. The Chip contains the following separate circuits circuits:
A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load.
NAND and NOR gates using 6u/0.6u NMOSs and PMOSs.
An inverter made with a 6u/0.6u NMOS and a 12/0.6 PMOS.
6u/0.6u 4-terminal PMOS transistor.
6u/0.6u 4-terminal NMOS transistor.
A 25k-10k resistor voltage divider.
An 8 bit serial to parallel converter.
Chip Schematic:
Chip Layout:
DRC and LVS
Pin Connections:
Pin 20 is Ground for all circuits.
31-stage Oscillator Pinout:
|
Pin |
Connection |
|
<1> |
osc_out |
|
<2> |
VDD |
NAND gate Pinout:
|
PIN |
Connection |
|
<22> |
A |
|
<21> |
B |
|
<23> |
AnandB |
|
<40> |
VDD |
NOR gate Pinout:
|
Pin |
Connection |
|
<36> |
A |
|
<37> |
B |
|
<38> |
AnorB |
|
<39> |
VDD |
Inverter gate Pinout:
|
Pin |
Connection |
|
<15> |
A |
|
<16> |
Ai |
|
<17> |
VDD |
25k-10k resistor Voltage divider:
|
Pin |
Connection |
|
<5> |
in |
|
<4> |
out |
NMOS
transistor:
|
Pin |
Connection |
|
<7> |
D |
|
<8> |
G |
|
<9> |
S |
|
<20> |
body(gnd!) |
PMOS transistor:
|
Pin |
Connection |
|
<11> |
S |
|
<12> |
G |
|
<13> |
D |
|
<14> |
body |
Serial to Parallel converter:
|
Pin |
Connections |
|
<24> |
VDD |
|
<25> |
Din |
|
<26> |
Clk_in |
|
<27> |
D7 |
|
<28> |
D6 |
|
<29> |
D5 |
|
<31> |
D3 |
|
<32> |
D2 |
|
<33> |
D1 |
|
<34> |
D0 |
|
<35> |
Clk_out |
Design File HERE
