Lab 7 - EE 421L
Author: David Silic
Email: silic@unlv.nevada.edu
EE421L
For the Prelab we went through the tutorial to design and simulate a 32 but Oscillator.
Oscillator with individual inverters.
Condensed
schematic and Simulation below:
Layout, DRC and LVS of the 32 bit oscillator circuit above
Main Lab For the main lab we first design a 4-bit inverter schematic.
Now we proceed to simulate the circuit.
Note how all four outputs are inverted from the input(top trace).
Now we proceed to use the same method for an 8-bit inverter:
Just
like the 4 bit version the each bit is inverted from the input.
Next we design a NAND gate.
Using the above circuit we design an 8-bit NAND and proceed to simulate.
Note the output is only 0 when A and B are both 1, as we see on the last 4th of the graph.
Here we follow the same process as the NAND for the NOR gate. Here the output is only 1 when A and B are both 0, which only occurs for the first 4th of the simulation.
Next be build an OR gate, by simply aadding an inverter to our existing NOR schematic:
Here we see the output value is only zero when both inputs are zero.
A similar process is used for the AND gate seen below:
Now we must build our 2-1 Mux
we
use the following schematic and symbol:
Simulation for the Mux:
Note how the output(pink trace) follows B(blue trace) when selector(Orange trace) is low. When the selector is high the output follows A(red trace).
Now we build an 8 bit version, note how we use an inverter to allow us to generate S* without an extra input necessary.
As with the previous sim we note that the 8-bit outputs follow B for S low and follow A when S is high.
Now
we design our Full adder using schematic 12.20 from the book
Now we design an 8 bit version and simulate it:
In our simulation we add 11111111 and 00100000 with a carry in of 1. We choose those numbers to make it easy to see that we are getting the correct value out.
We note that the calculation is as follows:
|
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
+ + + + + + + +
|
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
=
|
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
And we get a carry out of 1.
Here we can clearly see the correct output given as calculated from the above table.
Now the job remaining is to layout the circuit.
We first build a single full adder:
DRC:
And LVS:
And the LVS shows matching net-lists.
Now we build the entire 8-bit Full Adder:
The layout is a bit hard to see because of the size. Below is a portion of the layout:
Now we DRC and LVS:
Every thing checks out! We back everything up on Google and PC as usual.
