Lab 6 - EE 421L
Author: David Silic
Email: silic@unlv.nevada.edu
EE421L
The prelab work mostly consisted of completing Tutorial 4 which deals with simulation and layout of a two-input NAND gate.
The completed Layout and schematic I used is pictured below:
DRC checked out.
Main Lab Work
For the lab work we built a full adder using NAND and XOR gates.
First we built and simulated the necessary gates, once that was complete we were able to design and layout the Full adder.
The layout, DRC, and LVS of the NAND was already done in the prelab as depicted above, thus we now must build the Xor gate using the schematic shown below:
Layout:
Note the Inverters are on the right and left side while the 4 PMOS are on top and the 4 NMOS are below:
DRC:
Now we must simulate our gates with a simple test schematic:
Here we have two pulses connected to the A and B inputs of our inverter, NAND, and XOR gates.
The simulations designed to represent the following truth table:
|
A |
B |
Ai |
AxorB |
AnandB |
|
0 |
0 |
1 |
0 |
1 |
|
0 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
1 |
|
1 |
1 |
0 |
0 |
0 |
The top two traces represent A and B inputs, pink represents A inverted, Green AxorB and Orenge represents AnandB. Each 100n represents 1 clock cycle, note how A is low for the first 200n and goes high for the following 200ns as the truth table dictates. As expected Ai is invers of A, AxorB is low for A=B, but high when A =/= B. AnandB is low only when A and B are both high.
Now we may proceed to creating our Full Adder. We use the following schematic:
Which may be abstraced to the following symbol:
Now we are ready to for the layout:
DRC
checks out.
Success!!
Finally we must sim
the Full adder circuit. We use a similar method to as we used for the
NAND sim. 
This time we will use 1u for each clock cycle, thus our sim will run for 8u.
We utilize the following truth table:
Each trace represents a column from the truth table, note how sum(brown) has the pattern 0,1,1,0,1,0,0,1 as expected from the truth table. Similarly Cout has the sequence 0,0,0,1,0,1,1,1 which also matches.
This completes our lab, as usual the I backed up my lab files both on my PC and on google drive:
Zip file containing design files HERE
