Lab 5 - ECE 421L
Author: David Silic
Email: silic@unlv.nevada.edu
EE421L
This Prelab focuses on design and simulation of an Inverter circuit as explained by Tutorial 3.
Pictured below the final step is of tutorial 1 is a simulation of the inverter circuit.
Lab report:
For
this lab we will design and simulate two inverters of different
sizes, a 12u/6u and a 48u/24u. We instantiate a PMOS and an NMOS and
set the dimensions for 12u/6u as shown below:
For the 48/24u inverter we simply
use the same circuit but set the multiplier to 4.
Now we create the layout for each circuit inverter:
Layout and Extracted view for the 12u/6u inverter shown above.
Now we begin the DRC and LVS process.
DRC:
LVS:
Now we follow the same process
for the 48/24u inverter, the layout requires 4 fingers with the same
width and length dimensions:
shown above.
Net
lists match.
Now we take the inverters and simulate each circuit with various capacitive loads. We will use both our normal specter sim and an UltraSim.
12u/6u circuit:
We set the capacitor to a variable and simulate a parametric analysis from 100fF to 100pF using a decade sweep. This simulates gives the following:
Normal sim.
UltraSim
For both sims the graph represents the following voltages:
Blue = Vout at 100f F
Pink
= Vout at1p F
green = Vout at 10p F
light blue = Vout at 100P F
red = VIN
Now we follow the same process using the 48u/12u Inverter:
UltraSim.
The Graphs follow the same convention as the first circuit:
Blue = Vout at 100f F
Pink
= Vout at 1p F
green = Vout at 10p F
light blue = Vout at 100P F
red = VIN
This
completes the lab report.
This lab successfully explored how build
the schematic, layout and simulation for inverter circuits.
As usual I back up the files on my PC as well as Google drive.
Zip file containing design files HERE
